forked from Minki/linux
b244ffa15c
Physical plane's tiling mode value is given directly as
drm_format_mod for plane query, which is not correct fourcc
code. Fix it by using correct intel tiling fourcc mod definition.
Current qemu seems also doesn't correctly utilize drm_format_mod
for plane object setting. Anyway this is required to fix the usage.
v3: use DRM_FORMAT_MOD_LINEAR, fix comment
v2: Fix missed old 'tiled' use for stride calculation
Fixes: e546e281d3 ("drm/i915/gvt: Dmabuf support for GVT-g")
Cc: Tina Zhang <tina.zhang@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Colin Xu <Colin.Xu@intel.com>
Reviewed-by: Colin Xu <Colin.Xu@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
170 lines
5.8 KiB
C
170 lines
5.8 KiB
C
/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Kevin Tian <kevin.tian@intel.com>
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*
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* Contributors:
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* Bing Niu <bing.niu@intel.com>
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* Xu Han <xu.han@intel.com>
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* Ping Gao <ping.a.gao@intel.com>
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* Xiaoguang Chen <xiaoguang.chen@intel.com>
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* Yang Liu <yang2.liu@intel.com>
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* Tina Zhang <tina.zhang@intel.com>
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*
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*/
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#ifndef _GVT_FB_DECODER_H_
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#define _GVT_FB_DECODER_H_
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#define _PLANE_CTL_FORMAT_SHIFT 24
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#define _PLANE_CTL_TILED_SHIFT 10
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#define _PIPE_V_SRCSZ_SHIFT 0
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#define _PIPE_V_SRCSZ_MASK (0xfff << _PIPE_V_SRCSZ_SHIFT)
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#define _PIPE_H_SRCSZ_SHIFT 16
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#define _PIPE_H_SRCSZ_MASK (0x1fff << _PIPE_H_SRCSZ_SHIFT)
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#define _PRI_PLANE_FMT_SHIFT 26
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#define _PRI_PLANE_STRIDE_MASK (0x3ff << 6)
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#define _PRI_PLANE_X_OFF_SHIFT 0
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#define _PRI_PLANE_X_OFF_MASK (0x1fff << _PRI_PLANE_X_OFF_SHIFT)
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#define _PRI_PLANE_Y_OFF_SHIFT 16
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#define _PRI_PLANE_Y_OFF_MASK (0xfff << _PRI_PLANE_Y_OFF_SHIFT)
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#define _CURSOR_MODE 0x3f
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#define _CURSOR_ALPHA_FORCE_SHIFT 8
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#define _CURSOR_ALPHA_FORCE_MASK (0x3 << _CURSOR_ALPHA_FORCE_SHIFT)
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#define _CURSOR_ALPHA_PLANE_SHIFT 10
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#define _CURSOR_ALPHA_PLANE_MASK (0x3 << _CURSOR_ALPHA_PLANE_SHIFT)
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#define _CURSOR_POS_X_SHIFT 0
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#define _CURSOR_POS_X_MASK (0x1fff << _CURSOR_POS_X_SHIFT)
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#define _CURSOR_SIGN_X_SHIFT 15
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#define _CURSOR_SIGN_X_MASK (1 << _CURSOR_SIGN_X_SHIFT)
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#define _CURSOR_POS_Y_SHIFT 16
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#define _CURSOR_POS_Y_MASK (0xfff << _CURSOR_POS_Y_SHIFT)
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#define _CURSOR_SIGN_Y_SHIFT 31
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#define _CURSOR_SIGN_Y_MASK (1 << _CURSOR_SIGN_Y_SHIFT)
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#define _SPRITE_FMT_SHIFT 25
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#define _SPRITE_COLOR_ORDER_SHIFT 20
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#define _SPRITE_YUV_ORDER_SHIFT 16
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#define _SPRITE_STRIDE_SHIFT 6
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#define _SPRITE_STRIDE_MASK (0x1ff << _SPRITE_STRIDE_SHIFT)
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#define _SPRITE_SIZE_WIDTH_SHIFT 0
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#define _SPRITE_SIZE_HEIGHT_SHIFT 16
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#define _SPRITE_SIZE_WIDTH_MASK (0x1fff << _SPRITE_SIZE_WIDTH_SHIFT)
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#define _SPRITE_SIZE_HEIGHT_MASK (0xfff << _SPRITE_SIZE_HEIGHT_SHIFT)
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#define _SPRITE_POS_X_SHIFT 0
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#define _SPRITE_POS_Y_SHIFT 16
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#define _SPRITE_POS_X_MASK (0x1fff << _SPRITE_POS_X_SHIFT)
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#define _SPRITE_POS_Y_MASK (0xfff << _SPRITE_POS_Y_SHIFT)
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#define _SPRITE_OFFSET_START_X_SHIFT 0
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#define _SPRITE_OFFSET_START_Y_SHIFT 16
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#define _SPRITE_OFFSET_START_X_MASK (0x1fff << _SPRITE_OFFSET_START_X_SHIFT)
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#define _SPRITE_OFFSET_START_Y_MASK (0xfff << _SPRITE_OFFSET_START_Y_SHIFT)
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enum GVT_FB_EVENT {
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FB_MODE_SET_START = 1,
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FB_MODE_SET_END,
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FB_DISPLAY_FLIP,
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};
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enum DDI_PORT {
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DDI_PORT_NONE = 0,
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DDI_PORT_B = 1,
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DDI_PORT_C = 2,
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DDI_PORT_D = 3,
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DDI_PORT_E = 4
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};
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struct intel_gvt;
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/* color space conversion and gamma correction are not included */
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struct intel_vgpu_primary_plane_format {
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u8 enabled; /* plane is enabled */
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u32 tiled; /* tiling mode: linear, X-tiled, Y tiled, etc */
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u8 bpp; /* bits per pixel */
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u32 hw_format; /* format field in the PRI_CTL register */
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u32 drm_format; /* format in DRM definition */
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u32 base; /* framebuffer base in graphics memory */
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u64 base_gpa;
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u32 x_offset; /* in pixels */
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u32 y_offset; /* in lines */
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u32 width; /* in pixels */
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u32 height; /* in lines */
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u32 stride; /* in bytes */
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};
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struct intel_vgpu_sprite_plane_format {
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u8 enabled; /* plane is enabled */
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u8 tiled; /* X-tiled */
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u8 bpp; /* bits per pixel */
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u32 hw_format; /* format field in the SPR_CTL register */
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u32 drm_format; /* format in DRM definition */
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u32 base; /* sprite base in graphics memory */
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u64 base_gpa;
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u32 x_pos; /* in pixels */
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u32 y_pos; /* in lines */
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u32 x_offset; /* in pixels */
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u32 y_offset; /* in lines */
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u32 width; /* in pixels */
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u32 height; /* in lines */
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u32 stride; /* in bytes */
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};
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struct intel_vgpu_cursor_plane_format {
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u8 enabled;
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u8 mode; /* cursor mode select */
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u8 bpp; /* bits per pixel */
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u32 drm_format; /* format in DRM definition */
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u32 base; /* cursor base in graphics memory */
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u64 base_gpa;
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u32 x_pos; /* in pixels */
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u32 y_pos; /* in lines */
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u8 x_sign; /* X Position Sign */
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u8 y_sign; /* Y Position Sign */
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u32 width; /* in pixels */
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u32 height; /* in lines */
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u32 x_hot; /* in pixels */
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u32 y_hot; /* in pixels */
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};
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struct intel_vgpu_pipe_format {
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struct intel_vgpu_primary_plane_format primary;
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struct intel_vgpu_sprite_plane_format sprite;
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struct intel_vgpu_cursor_plane_format cursor;
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enum DDI_PORT ddi_port; /* the DDI port that pipe is connected to */
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};
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struct intel_vgpu_fb_format {
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struct intel_vgpu_pipe_format pipes[I915_MAX_PIPES];
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};
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int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
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struct intel_vgpu_primary_plane_format *plane);
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int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
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struct intel_vgpu_cursor_plane_format *plane);
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int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,
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struct intel_vgpu_sprite_plane_format *plane);
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#endif
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