518b466a21
These Socs have 1-3 banks of 8-32 gpios. Rather then setting the muxing of each pin individually, these socs have mux groups that when set will effect 1-N pins. Pin groups have a 2, 4 or 8 different muxes. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20201208075523.7060-3-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
15 lines
336 B
Plaintext
15 lines
336 B
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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menu "Ralink pinctrl drivers"
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depends on RALINK
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config PINCTRL_RALINK
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bool "Ralink pin control support"
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default y if RALINK
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config PINCTRL_RT2880
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bool "RT2880 pinctrl driver for RALINK/Mediatek SOCs"
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select PINMUX
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select GENERIC_PINCONF
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endmenu
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