c6538de8dd
Add DSI PLL common clock framework clocks for 8960 PHY. The PLL here is different from the ones found in B family msm chips. As before, the DSI provides two clocks to the outside world. dsixpll and dsixpllbyte (x = 1, 2). dsixpll is a regular clock divider, but dsixpllbyte is modelled as a custom clock divider. dsixpllbyte is the starting point of the PLL configuration. It is the one that sets up the VCO clock rate. We need the VCO clock rate in the form: F * byteclk, where F is a multiplication factor that varies on the byte clock the DSI driver is trying to set. We use the custom clk_ops for dsixpllbyte to ensure that the parent (VCO) is set at this rate. An additional divider (POSTDIV1) generates the bitclk. Since bit clock can be derived from byteclock, we calculate it internally, and don't expose it as a clock. Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
109 lines
2.8 KiB
C
109 lines
2.8 KiB
C
/*
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* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DSI_PLL_H__
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#define __DSI_PLL_H__
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include "dsi.h"
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#define NUM_DSI_CLOCKS_MAX 6
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#define MAX_DSI_PLL_EN_SEQS 10
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struct msm_dsi_pll {
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enum msm_dsi_phy_type type;
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struct clk_hw clk_hw;
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bool pll_on;
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bool state_saved;
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unsigned long min_rate;
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unsigned long max_rate;
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u32 en_seq_cnt;
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int (*enable_seqs[MAX_DSI_PLL_EN_SEQS])(struct msm_dsi_pll *pll);
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void (*disable_seq)(struct msm_dsi_pll *pll);
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int (*get_provider)(struct msm_dsi_pll *pll,
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struct clk **byte_clk_provider,
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struct clk **pixel_clk_provider);
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void (*destroy)(struct msm_dsi_pll *pll);
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void (*save_state)(struct msm_dsi_pll *pll);
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int (*restore_state)(struct msm_dsi_pll *pll);
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};
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#define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw)
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static inline void pll_write(void __iomem *reg, u32 data)
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{
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msm_writel(data, reg);
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}
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static inline u32 pll_read(const void __iomem *reg)
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{
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return msm_readl(reg);
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}
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static inline void pll_write_udelay(void __iomem *reg, u32 data, u32 delay_us)
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{
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pll_write(reg, data);
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udelay(delay_us);
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}
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static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns)
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{
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pll_write((reg), data);
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ndelay(delay_ns);
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}
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/*
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* DSI PLL Helper functions
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*/
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/* clock callbacks */
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long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long *parent_rate);
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int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw);
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void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw);
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/* misc */
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void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev,
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struct clk **clks, u32 num_clks);
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/*
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* Initialization for Each PLL Type
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*/
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#ifdef CONFIG_DRM_MSM_DSI_28NM_PHY
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struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
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enum msm_dsi_phy_type type, int id);
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#else
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static inline struct msm_dsi_pll *msm_dsi_pll_28nm_init(
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struct platform_device *pdev, enum msm_dsi_phy_type type, int id)
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{
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return ERR_PTR(-ENODEV);
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}
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#endif
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#ifdef CONFIG_DRM_MSM_DSI_28NM_8960_PHY
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struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev,
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int id);
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#else
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struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev,
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int id)
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{
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return ERR_PTR(-ENODEV);
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}
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#endif
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#endif /* __DSI_PLL_H__ */
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