forked from Minki/linux
4afe2d1a6e
The JZ4780's MSC clock divider registers multiply the clock divider by 2. This means that MMC devices run at half their expected speed. Add the ability to divide the clock divider in order to solve this. Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
304 lines
7.5 KiB
C
304 lines
7.5 KiB
C
/*
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* Ingenic JZ4740 SoC CGU driver
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*
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* Copyright (c) 2015 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <dt-bindings/clock/jz4740-cgu.h>
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#include <asm/mach-jz4740/clock.h>
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#include "cgu.h"
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/* CGU register offsets */
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#define CGU_REG_CPCCR 0x00
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#define CGU_REG_LCR 0x04
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#define CGU_REG_CPPCR 0x10
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#define CGU_REG_CLKGR 0x20
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#define CGU_REG_SCR 0x24
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#define CGU_REG_I2SCDR 0x60
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#define CGU_REG_LPCDR 0x64
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#define CGU_REG_MSCCDR 0x68
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#define CGU_REG_UHCCDR 0x6c
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#define CGU_REG_SSICDR 0x74
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/* bits within a PLL control register */
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#define PLLCTL_M_SHIFT 23
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#define PLLCTL_M_MASK (0x1ff << PLLCTL_M_SHIFT)
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#define PLLCTL_N_SHIFT 18
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#define PLLCTL_N_MASK (0x1f << PLLCTL_N_SHIFT)
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#define PLLCTL_OD_SHIFT 16
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#define PLLCTL_OD_MASK (0x3 << PLLCTL_OD_SHIFT)
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#define PLLCTL_STABLE (1 << 10)
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#define PLLCTL_BYPASS (1 << 9)
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#define PLLCTL_ENABLE (1 << 8)
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/* bits within the LCR register */
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#define LCR_SLEEP (1 << 0)
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/* bits within the CLKGR register */
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#define CLKGR_UDC (1 << 11)
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static struct ingenic_cgu *cgu;
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static const s8 pll_od_encoding[4] = {
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0x0, 0x1, -1, 0x3,
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};
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static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
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/* External clocks */
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[JZ4740_CLK_EXT] = { "ext", CGU_CLK_EXT },
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[JZ4740_CLK_RTC] = { "rtc", CGU_CLK_EXT },
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[JZ4740_CLK_PLL] = {
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"pll", CGU_CLK_PLL,
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.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
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.pll = {
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.reg = CGU_REG_CPPCR,
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.m_shift = 23,
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.m_bits = 9,
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.m_offset = 2,
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.n_shift = 18,
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.n_bits = 5,
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.n_offset = 2,
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.od_shift = 16,
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.od_bits = 2,
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.od_max = 4,
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.od_encoding = pll_od_encoding,
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.stable_bit = 10,
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.bypass_bit = 9,
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.enable_bit = 8,
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},
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},
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/* Muxes & dividers */
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[JZ4740_CLK_PLL_HALF] = {
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"pll half", CGU_CLK_DIV,
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1 },
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},
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[JZ4740_CLK_CCLK] = {
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"cclk", CGU_CLK_DIV,
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
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},
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[JZ4740_CLK_HCLK] = {
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"hclk", CGU_CLK_DIV,
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
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},
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[JZ4740_CLK_PCLK] = {
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"pclk", CGU_CLK_DIV,
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1 },
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},
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[JZ4740_CLK_MCLK] = {
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"mclk", CGU_CLK_DIV,
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1 },
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},
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[JZ4740_CLK_LCD] = {
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"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
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.div = { CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1 },
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.gate = { CGU_REG_CLKGR, 10 },
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},
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[JZ4740_CLK_LCD_PCLK] = {
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"lcd_pclk", CGU_CLK_DIV,
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.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
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.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
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},
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[JZ4740_CLK_I2S] = {
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"i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
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.mux = { CGU_REG_CPCCR, 31, 1 },
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.div = { CGU_REG_I2SCDR, 0, 1, 8, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 6 },
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},
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[JZ4740_CLK_SPI] = {
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"spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 },
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.mux = { CGU_REG_SSICDR, 31, 1 },
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.div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 4 },
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},
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[JZ4740_CLK_MMC] = {
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"mmc", CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
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.div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 7 },
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},
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[JZ4740_CLK_UHC] = {
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"uhc", CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
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.div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 14 },
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},
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[JZ4740_CLK_UDC] = {
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"udc", CGU_CLK_MUX | CGU_CLK_DIV,
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.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
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.mux = { CGU_REG_CPCCR, 29, 1 },
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.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
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.gate = { CGU_REG_SCR, 6 },
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},
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/* Gate-only clocks */
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[JZ4740_CLK_UART0] = {
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"uart0", CGU_CLK_GATE,
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.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 0 },
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},
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[JZ4740_CLK_UART1] = {
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"uart1", CGU_CLK_GATE,
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.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 15 },
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},
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[JZ4740_CLK_DMA] = {
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"dma", CGU_CLK_GATE,
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.parents = { JZ4740_CLK_PCLK, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 12 },
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},
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[JZ4740_CLK_IPU] = {
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"ipu", CGU_CLK_GATE,
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.parents = { JZ4740_CLK_PCLK, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 13 },
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},
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[JZ4740_CLK_ADC] = {
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"adc", CGU_CLK_GATE,
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.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 8 },
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},
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[JZ4740_CLK_I2C] = {
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"i2c", CGU_CLK_GATE,
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.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 3 },
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},
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[JZ4740_CLK_AIC] = {
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"aic", CGU_CLK_GATE,
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.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 5 },
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},
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};
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static void __init jz4740_cgu_init(struct device_node *np)
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{
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int retval;
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cgu = ingenic_cgu_new(jz4740_cgu_clocks,
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ARRAY_SIZE(jz4740_cgu_clocks), np);
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if (!cgu) {
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pr_err("%s: failed to initialise CGU\n", __func__);
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return;
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}
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retval = ingenic_cgu_register_clocks(cgu);
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if (retval)
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pr_err("%s: failed to register CGU Clocks\n", __func__);
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}
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CLK_OF_DECLARE(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);
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void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode)
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{
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uint32_t lcr = readl(cgu->base + CGU_REG_LCR);
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switch (mode) {
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case JZ4740_WAIT_MODE_IDLE:
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lcr &= ~LCR_SLEEP;
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break;
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case JZ4740_WAIT_MODE_SLEEP:
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lcr |= LCR_SLEEP;
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break;
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}
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writel(lcr, cgu->base + CGU_REG_LCR);
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}
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void jz4740_clock_udc_disable_auto_suspend(void)
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{
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uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR);
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clkgr &= ~CLKGR_UDC;
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writel(clkgr, cgu->base + CGU_REG_CLKGR);
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}
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EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend);
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void jz4740_clock_udc_enable_auto_suspend(void)
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{
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uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR);
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clkgr |= CLKGR_UDC;
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writel(clkgr, cgu->base + CGU_REG_CLKGR);
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}
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EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend);
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#define JZ_CLOCK_GATE_UART0 BIT(0)
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#define JZ_CLOCK_GATE_TCU BIT(1)
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#define JZ_CLOCK_GATE_DMAC BIT(12)
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void jz4740_clock_suspend(void)
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{
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uint32_t clkgr, cppcr;
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clkgr = readl(cgu->base + CGU_REG_CLKGR);
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clkgr |= JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0;
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writel(clkgr, cgu->base + CGU_REG_CLKGR);
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cppcr = readl(cgu->base + CGU_REG_CPPCR);
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cppcr &= ~BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.enable_bit);
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writel(cppcr, cgu->base + CGU_REG_CPPCR);
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}
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void jz4740_clock_resume(void)
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{
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uint32_t clkgr, cppcr, stable;
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cppcr = readl(cgu->base + CGU_REG_CPPCR);
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cppcr |= BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.enable_bit);
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writel(cppcr, cgu->base + CGU_REG_CPPCR);
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stable = BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.stable_bit);
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do {
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cppcr = readl(cgu->base + CGU_REG_CPPCR);
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} while (!(cppcr & stable));
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clkgr = readl(cgu->base + CGU_REG_CLKGR);
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clkgr &= ~JZ_CLOCK_GATE_TCU;
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clkgr &= ~JZ_CLOCK_GATE_DMAC;
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clkgr &= ~JZ_CLOCK_GATE_UART0;
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writel(clkgr, cgu->base + CGU_REG_CLKGR);
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}
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