forked from Minki/linux
cd4f2d4aa7
This patch configures the I2C bus timing registers according to information passed via DT. Currently, 100kHz and 400kHz modes are supported. The TIMING2 register value is wrong in the documentation for i.MX28! This was found and fixed by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
20 lines
525 B
Plaintext
20 lines
525 B
Plaintext
* Freescale MXS Inter IC (I2C) Controller
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Required properties:
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- compatible: Should be "fsl,<chip>-i2c"
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- reg: Should contain registers location and length
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- interrupts: Should contain ERROR and DMA interrupts
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- clock-frequency: Desired I2C bus clock frequency in Hz.
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Only 100000Hz and 400000Hz modes are supported.
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Examples:
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i2c0: i2c@80058000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx28-i2c";
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reg = <0x80058000 2000>;
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interrupts = <111 68>;
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clock-frequency = <100000>;
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};
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