forked from Minki/linux
ae0add740c
This change makes the DT file to be easier to read since the reserved slots array does not need the '/bits/ 16' to be specified, which might confuse some people. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
149 lines
4.6 KiB
Plaintext
149 lines
4.6 KiB
Plaintext
Texas Instruments eDMA
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The eDMA3 consists of two components: Channel controller (CC) and Transfer
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Controller(s) (TC). The CC is the main entry for DMA users since it is
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responsible for the DMA channel handling, while the TCs are responsible to
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execute the actual DMA tansfer.
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------------------------------------------------------------------------------
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eDMA3 Channel Controller
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Required properties:
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- compatible: "ti,edma3-tpcc" for the channel controller(s)
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- #dma-cells: Should be set to <2>. The first number is the DMA request
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number and the second is the TC the channel is serviced on.
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- reg: Memory map of eDMA CC
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- reg-names: "edma3_cc"
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- interrupts: Interrupt lines for CCINT, MPERR and CCERRINT.
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- interrupt-names: "edma3_ccint", "emda3_mperr" and "edma3_ccerrint"
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- ti,tptcs: List of TPTCs associated with the eDMA in the following form:
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<&tptc_phandle TC_priority_number>. The highest priority is 0.
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Optional properties:
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- ti,hwmods: Name of the hwmods associated to the eDMA CC
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- ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
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these channels will be SW triggered channels. See example.
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- ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
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the driver, they are allocated to be used by for example the
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DSP. See example.
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------------------------------------------------------------------------------
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eDMA3 Transfer Controller
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Required properties:
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- compatible: "ti,edma3-tptc" for the transfer controller(s)
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- reg: Memory map of eDMA TC
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- interrupts: Interrupt number for TCerrint.
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Optional properties:
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- ti,hwmods: Name of the hwmods associated to the given eDMA TC
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- interrupt-names: "edma3_tcerrint"
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------------------------------------------------------------------------------
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Example:
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edma: edma@49000000 {
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compatible = "ti,edma3-tpcc";
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ti,hwmods = "tpcc";
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reg = <0x49000000 0x10000>;
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reg-names = "edma3_cc";
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interrupts = <12 13 14>;
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interrupt-names = "edma3_ccint", "emda3_mperr", "edma3_ccerrint";
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dma-requests = <64>;
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#dma-cells = <2>;
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ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 7>, <&edma_tptc2 0>;
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/* Channel 20 and 21 is allocated for memcpy */
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ti,edma-memcpy-channels = <20 21>;
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/* The following PaRAM slots are reserved: 35-44 and 100-109 */
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ti,edma-reserved-slot-ranges = <35 10>, <100 10>;
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};
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edma_tptc0: tptc@49800000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc0";
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reg = <0x49800000 0x100000>;
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interrupts = <112>;
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interrupt-names = "edm3_tcerrint";
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};
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edma_tptc1: tptc@49900000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc1";
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reg = <0x49900000 0x100000>;
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interrupts = <113>;
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interrupt-names = "edm3_tcerrint";
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};
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edma_tptc2: tptc@49a00000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc2";
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reg = <0x49a00000 0x100000>;
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interrupts = <114>;
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interrupt-names = "edm3_tcerrint";
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};
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sham: sham@53100000 {
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compatible = "ti,omap4-sham";
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ti,hwmods = "sham";
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reg = <0x53100000 0x200>;
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interrupts = <109>;
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/* DMA channel 36 executed on eDMA TC0 - low priority queue */
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dmas = <&edma 36 0>;
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dma-names = "rx";
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};
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mcasp0: mcasp@48038000 {
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compatible = "ti,am33xx-mcasp-audio";
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ti,hwmods = "mcasp0";
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reg = <0x48038000 0x2000>,
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<0x46000000 0x400000>;
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reg-names = "mpu", "dat";
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interrupts = <80>, <81>;
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interrupt-names = "tx", "rx";
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status = "disabled";
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/* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */
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dmas = <&edma 8 2>,
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<&edma 9 2>;
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dma-names = "tx", "rx";
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};
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------------------------------------------------------------------------------
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DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc
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binding.
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Required properties:
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- compatible : "ti,edma3"
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- #dma-cells: Should be set to <1>
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Clients should use a single channel number per DMA request.
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- reg: Memory map for accessing module
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- interrupt-parent: Interrupt controller the interrupt is routed through
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- interrupts: Exactly 3 interrupts need to be specified in the order:
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1. Transfer completion interrupt.
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2. Memory protection interrupt.
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3. Error interrupt.
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Optional properties:
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- ti,hwmods: Name of the hwmods associated to the EDMA
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- ti,edma-xbar-event-map: Crossbar event to channel map
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Deprecated properties:
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Listed here in case one wants to boot an old kernel with new DTB. These
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properties might need to be added to the new DTS files.
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- ti,edma-regions: Number of regions
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- ti,edma-slots: Number of slots
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- dma-channels: Specify total DMA channels per CC
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Example:
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edma: edma@49000000 {
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reg = <0x49000000 0x10000>;
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interrupt-parent = <&intc>;
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interrupts = <12 13 14>;
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compatible = "ti,edma3";
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ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
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#dma-cells = <1>;
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ti,edma-xbar-event-map = /bits/ 16 <1 12
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2 13>;
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};
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