forked from Minki/linux
f96a8a0b78
This patch adds new initialization functions and device support for i210 and i211 devices. Signed-off-by: Carolyn Wyborny <carolyn.wyborny@intel.com> Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
386 lines
10 KiB
C
386 lines
10 KiB
C
/*
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* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
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*
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* Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/pci.h>
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#include "igb.h"
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#define INCVALUE_MASK 0x7fffffff
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#define ISGN 0x80000000
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/*
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* The 82580 timesync updates the system timer every 8ns by 8ns,
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* and this update value cannot be reprogrammed.
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*
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* Neither the 82576 nor the 82580 offer registers wide enough to hold
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* nanoseconds time values for very long. For the 82580, SYSTIM always
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* counts nanoseconds, but the upper 24 bits are not availible. The
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* frequency is adjusted by changing the 32 bit fractional nanoseconds
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* register, TIMINCA.
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*
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* For the 82576, the SYSTIM register time unit is affect by the
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* choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
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* field are needed to provide the nominal 16 nanosecond period,
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* leaving 19 bits for fractional nanoseconds.
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*
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* We scale the NIC clock cycle by a large factor so that relatively
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* small clock corrections can be added or subtracted at each clock
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* tick. The drawbacks of a large factor are a) that the clock
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* register overflows more quickly (not such a big deal) and b) that
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* the increment per tick has to fit into 24 bits. As a result we
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* need to use a shift of 19 so we can fit a value of 16 into the
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* TIMINCA register.
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*
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*
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* SYSTIMH SYSTIML
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* +--------------+ +---+---+------+
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* 82576 | 32 | | 8 | 5 | 19 |
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* +--------------+ +---+---+------+
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* \________ 45 bits _______/ fract
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*
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* +----------+---+ +--------------+
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* 82580 | 24 | 8 | | 32 |
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* +----------+---+ +--------------+
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* reserved \______ 40 bits _____/
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*
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*
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* The 45 bit 82576 SYSTIM overflows every
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* 2^45 * 10^-9 / 3600 = 9.77 hours.
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*
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* The 40 bit 82580 SYSTIM overflows every
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* 2^40 * 10^-9 / 60 = 18.3 minutes.
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*/
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#define IGB_OVERFLOW_PERIOD (HZ * 60 * 9)
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#define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
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#define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1)
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#define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
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#define IGB_NBITS_82580 40
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/*
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* SYSTIM read access for the 82576
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*/
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static cycle_t igb_82576_systim_read(const struct cyclecounter *cc)
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{
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u64 val;
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u32 lo, hi;
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struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
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struct e1000_hw *hw = &igb->hw;
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lo = rd32(E1000_SYSTIML);
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hi = rd32(E1000_SYSTIMH);
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val = ((u64) hi) << 32;
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val |= lo;
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return val;
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}
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/*
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* SYSTIM read access for the 82580
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*/
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static cycle_t igb_82580_systim_read(const struct cyclecounter *cc)
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{
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u64 val;
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u32 lo, hi, jk;
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struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
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struct e1000_hw *hw = &igb->hw;
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/*
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* The timestamp latches on lowest register read. For the 82580
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* the lowest register is SYSTIMR instead of SYSTIML. However we only
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* need to provide nanosecond resolution, so we just ignore it.
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*/
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jk = rd32(E1000_SYSTIMR);
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lo = rd32(E1000_SYSTIML);
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hi = rd32(E1000_SYSTIMH);
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val = ((u64) hi) << 32;
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val |= lo;
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return val;
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}
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/*
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* PTP clock operations
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*/
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static int ptp_82576_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
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{
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u64 rate;
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u32 incvalue;
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int neg_adj = 0;
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struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);
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struct e1000_hw *hw = &igb->hw;
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if (ppb < 0) {
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neg_adj = 1;
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ppb = -ppb;
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}
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rate = ppb;
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rate <<= 14;
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rate = div_u64(rate, 1953125);
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incvalue = 16 << IGB_82576_TSYNC_SHIFT;
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if (neg_adj)
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incvalue -= rate;
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else
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incvalue += rate;
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wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
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return 0;
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}
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static int ptp_82580_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
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{
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u64 rate;
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u32 inca;
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int neg_adj = 0;
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struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);
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struct e1000_hw *hw = &igb->hw;
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if (ppb < 0) {
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neg_adj = 1;
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ppb = -ppb;
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}
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rate = ppb;
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rate <<= 26;
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rate = div_u64(rate, 1953125);
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inca = rate & INCVALUE_MASK;
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if (neg_adj)
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inca |= ISGN;
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wr32(E1000_TIMINCA, inca);
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return 0;
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}
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static int igb_adjtime(struct ptp_clock_info *ptp, s64 delta)
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{
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s64 now;
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unsigned long flags;
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struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);
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spin_lock_irqsave(&igb->tmreg_lock, flags);
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now = timecounter_read(&igb->tc);
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now += delta;
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timecounter_init(&igb->tc, &igb->cc, now);
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spin_unlock_irqrestore(&igb->tmreg_lock, flags);
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return 0;
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}
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static int igb_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
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{
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u64 ns;
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u32 remainder;
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unsigned long flags;
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struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);
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spin_lock_irqsave(&igb->tmreg_lock, flags);
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ns = timecounter_read(&igb->tc);
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spin_unlock_irqrestore(&igb->tmreg_lock, flags);
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ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
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ts->tv_nsec = remainder;
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return 0;
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}
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static int igb_settime(struct ptp_clock_info *ptp, const struct timespec *ts)
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{
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u64 ns;
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unsigned long flags;
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struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);
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ns = ts->tv_sec * 1000000000ULL;
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ns += ts->tv_nsec;
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spin_lock_irqsave(&igb->tmreg_lock, flags);
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timecounter_init(&igb->tc, &igb->cc, ns);
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spin_unlock_irqrestore(&igb->tmreg_lock, flags);
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return 0;
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}
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static int ptp_82576_enable(struct ptp_clock_info *ptp,
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struct ptp_clock_request *rq, int on)
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{
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return -EOPNOTSUPP;
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}
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static int ptp_82580_enable(struct ptp_clock_info *ptp,
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struct ptp_clock_request *rq, int on)
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{
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return -EOPNOTSUPP;
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}
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static void igb_overflow_check(struct work_struct *work)
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{
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struct timespec ts;
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struct igb_adapter *igb =
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container_of(work, struct igb_adapter, overflow_work.work);
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igb_gettime(&igb->caps, &ts);
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pr_debug("igb overflow check at %ld.%09lu\n", ts.tv_sec, ts.tv_nsec);
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schedule_delayed_work(&igb->overflow_work, IGB_OVERFLOW_PERIOD);
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}
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void igb_ptp_init(struct igb_adapter *adapter)
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{
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struct e1000_hw *hw = &adapter->hw;
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switch (hw->mac.type) {
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case e1000_i210:
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case e1000_i211:
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case e1000_i350:
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case e1000_82580:
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adapter->caps.owner = THIS_MODULE;
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strcpy(adapter->caps.name, "igb-82580");
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adapter->caps.max_adj = 62499999;
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adapter->caps.n_ext_ts = 0;
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adapter->caps.pps = 0;
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adapter->caps.adjfreq = ptp_82580_adjfreq;
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adapter->caps.adjtime = igb_adjtime;
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adapter->caps.gettime = igb_gettime;
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adapter->caps.settime = igb_settime;
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adapter->caps.enable = ptp_82580_enable;
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adapter->cc.read = igb_82580_systim_read;
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adapter->cc.mask = CLOCKSOURCE_MASK(IGB_NBITS_82580);
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adapter->cc.mult = 1;
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adapter->cc.shift = 0;
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/* Enable the timer functions by clearing bit 31. */
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wr32(E1000_TSAUXC, 0x0);
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break;
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case e1000_82576:
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adapter->caps.owner = THIS_MODULE;
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strcpy(adapter->caps.name, "igb-82576");
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adapter->caps.max_adj = 1000000000;
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adapter->caps.n_ext_ts = 0;
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adapter->caps.pps = 0;
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adapter->caps.adjfreq = ptp_82576_adjfreq;
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adapter->caps.adjtime = igb_adjtime;
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adapter->caps.gettime = igb_gettime;
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adapter->caps.settime = igb_settime;
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adapter->caps.enable = ptp_82576_enable;
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adapter->cc.read = igb_82576_systim_read;
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adapter->cc.mask = CLOCKSOURCE_MASK(64);
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adapter->cc.mult = 1;
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adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
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/* Dial the nominal frequency. */
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wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
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break;
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default:
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adapter->ptp_clock = NULL;
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return;
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}
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wrfl();
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timecounter_init(&adapter->tc, &adapter->cc,
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ktime_to_ns(ktime_get_real()));
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INIT_DELAYED_WORK(&adapter->overflow_work, igb_overflow_check);
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spin_lock_init(&adapter->tmreg_lock);
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schedule_delayed_work(&adapter->overflow_work, IGB_OVERFLOW_PERIOD);
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adapter->ptp_clock = ptp_clock_register(&adapter->caps);
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if (IS_ERR(adapter->ptp_clock)) {
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adapter->ptp_clock = NULL;
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dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
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} else
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dev_info(&adapter->pdev->dev, "added PHC on %s\n",
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adapter->netdev->name);
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}
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void igb_ptp_remove(struct igb_adapter *adapter)
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{
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cancel_delayed_work_sync(&adapter->overflow_work);
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if (adapter->ptp_clock) {
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ptp_clock_unregister(adapter->ptp_clock);
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dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
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adapter->netdev->name);
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}
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}
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/**
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* igb_systim_to_hwtstamp - convert system time value to hw timestamp
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* @adapter: board private structure
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* @hwtstamps: timestamp structure to update
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* @systim: unsigned 64bit system time value.
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*
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* We need to convert the system time value stored in the RX/TXSTMP registers
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* into a hwtstamp which can be used by the upper level timestamping functions.
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*
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* The 'tmreg_lock' spinlock is used to protect the consistency of the
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* system time value. This is needed because reading the 64 bit time
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* value involves reading two (or three) 32 bit registers. The first
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* read latches the value. Ditto for writing.
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*
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* In addition, here have extended the system time with an overflow
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* counter in software.
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**/
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void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
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struct skb_shared_hwtstamps *hwtstamps,
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u64 systim)
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{
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u64 ns;
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unsigned long flags;
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switch (adapter->hw.mac.type) {
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case e1000_i210:
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case e1000_i211:
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case e1000_i350:
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case e1000_82580:
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case e1000_82576:
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break;
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default:
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return;
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}
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spin_lock_irqsave(&adapter->tmreg_lock, flags);
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ns = timecounter_cyc2time(&adapter->tc, systim);
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spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
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memset(hwtstamps, 0, sizeof(*hwtstamps));
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hwtstamps->hwtstamp = ns_to_ktime(ns);
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}
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