Hansen 5a1fef0278 drm/amd/display: Fix detection of 4 lane for DPALT ... [Why] DPALT detection for B0 PHY has its own set of RDPCSPIPE registers [How] Use RDPCSPIPE registers to detect if DPALT lane is 4 lane Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Hansen <Hansen.Dsouza@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org		2021-10-06 16:14:17 -04:00
..
amdgpu_dm	drm/amd/display: Pass PCI deviceid into DC	2021-09-28 14:39:54 -04:00
dc	drm/amd/display: Fix detection of 4 lane for DPALT	2021-10-06 16:14:17 -04:00
dmub	Kbuild updates for v5.15	2021-09-03 15:33:47 -07:00
include	drm/amd/display: USB4 bring up set correct address	2021-10-05 10:32:06 -04:00
modules	drm/amd: consolidate TA shared memory structures	2021-08-18 18:22:53 -04:00
Kconfig	drm/amdgpu/display: fix dependencies for DRM_AMD_DC_SI	2021-10-05 10:55:41 -04:00
Makefile
TODO