forked from Minki/linux
0fc9a6919c
Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property is used to disable rx detection in P3 PHY mode. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
665 lines
17 KiB
Plaintext
665 lines
17 KiB
Plaintext
/*
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* Device Tree Include file for Freescale Layerscape-1046A family SoC.
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*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* Mingkai Hu <mingkai.hu@nxp.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPLv2 or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "fsl,ls1046a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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crypto = &crypto;
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fman0 = &fman0;
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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ethernet3 = &enet3;
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ethernet4 = &enet4;
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ethernet5 = &enet5;
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ethernet6 = &enet6;
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ethernet7 = &enet7;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&l2>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x1>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&l2>;
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cpu-idle-states = <&CPU_PH20>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x2>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&l2>;
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cpu-idle-states = <&CPU_PH20>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x3>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&l2>;
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cpu-idle-states = <&CPU_PH20>;
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};
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l2: l2-cache {
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compatible = "cache";
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};
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};
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idle-states {
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/*
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* PSCI node is not added default, U-boot will add missing
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* parts if it determines to use PSCI.
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*/
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entry-method = "arm,psci";
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CPU_PH20: cpu-ph20 {
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compatible = "arm,idle-state";
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idle-state-name = "PH20";
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arm,psci-suspend-param = <0x00010000>;
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entry-latency-us = <1000>;
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exit-latency-us = <1000>;
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min-residency-us = <3000>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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};
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sysclk: sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "sysclk";
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};
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reboot {
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compatible ="syscon-reboot";
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regmap = <&dcfg>;
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offset = <0xb0>;
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mask = <0x02>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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compatible = "arm,cortex-a72-pmu";
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>,
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<&cpu1>,
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<&cpu2>,
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<&cpu3>;
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};
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gic: interrupt-controller@1400000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x1410000 0 0x10000>, /* GICD */
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<0x0 0x1420000 0 0x20000>, /* GICC */
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<0x0 0x1440000 0 0x20000>, /* GICH */
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<0x0 0x1460000 0 0x20000>; /* GICV */
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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ddr: memory-controller@1080000 {
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compatible = "fsl,qoriq-memory-controller";
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reg = <0x0 0x1080000 0x0 0x1000>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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big-endian;
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};
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ifc: ifc@1530000 {
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compatible = "fsl,ifc", "simple-bus";
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reg = <0x0 0x1530000 0x0 0x10000>;
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big-endian;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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};
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qspi: quadspi@1550000 {
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compatible = "fsl,ls1021a-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x1550000 0x0 0x10000>,
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<0x0 0x40000000 0x0 0x10000000>;
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reg-names = "QuadSPI", "QuadSPI-memory";
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "qspi_en", "qspi";
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clocks = <&clockgen 4 1>, <&clockgen 4 1>;
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big-endian;
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fsl,qspi-has-second-chip;
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status = "disabled";
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};
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esdhc: esdhc@1560000 {
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compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
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reg = <0x0 0x1560000 0x0 0x10000>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 2 1>;
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voltage-ranges = <1800 1800 3300 3300>;
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sdhci,auto-cmd12;
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big-endian;
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bus-width = <4>;
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};
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scfg: scfg@1570000 {
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compatible = "fsl,ls1046a-scfg", "syscon";
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reg = <0x0 0x1570000 0x0 0x10000>;
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big-endian;
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};
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crypto: crypto@1700000 {
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compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
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"fsl,sec-v4.0";
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fsl,sec-era = <8>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x00 0x1700000 0x100000>;
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reg = <0x00 0x1700000 0x0 0x100000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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sec_jr0: jr@10000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x10000 0x10000>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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};
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sec_jr1: jr@20000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x20000 0x10000>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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};
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sec_jr2: jr@30000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x30000 0x10000>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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};
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sec_jr3: jr@40000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x40000 0x10000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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qman: qman@1880000 {
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compatible = "fsl,qman";
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reg = <0x0 0x1880000 0x0 0x10000>;
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interrupts = <0 45 0x4>;
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memory-region = <&qman_fqd &qman_pfdr>;
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};
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bman: bman@1890000 {
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compatible = "fsl,bman";
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reg = <0x0 0x1890000 0x0 0x10000>;
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interrupts = <0 45 0x4>;
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memory-region = <&bman_fbpr>;
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};
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qportals: qman-portals@500000000 {
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ranges = <0x0 0x5 0x00000000 0x8000000>;
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};
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bportals: bman-portals@508000000 {
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ranges = <0x0 0x5 0x08000000 0x8000000>;
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};
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dcfg: dcfg@1ee0000 {
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compatible = "fsl,ls1046a-dcfg", "syscon";
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reg = <0x0 0x1ee0000 0x0 0x10000>;
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big-endian;
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};
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clockgen: clocking@1ee1000 {
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compatible = "fsl,ls1046a-clockgen";
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reg = <0x0 0x1ee1000 0x0 0x1000>;
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#clock-cells = <2>;
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clocks = <&sysclk>;
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};
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tmu: tmu@1f00000 {
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compatible = "fsl,qoriq-tmu";
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reg = <0x0 0x1f00000 0x0 0x10000>;
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interrupts = <0 33 0x4>;
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fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
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fsl,tmu-calibration =
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/* Calibration data group 1 */
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<0x00000000 0x00000026
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0x00000001 0x0000002d
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0x00000002 0x00000032
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0x00000003 0x00000039
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0x00000004 0x0000003f
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0x00000005 0x00000046
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0x00000006 0x0000004d
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0x00000007 0x00000054
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0x00000008 0x0000005a
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0x00000009 0x00000061
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0x0000000a 0x0000006a
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0x0000000b 0x00000071
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/* Calibration data group 2 */
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0x00010000 0x00000025
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0x00010001 0x0000002c
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0x00010002 0x00000035
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0x00010003 0x0000003d
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0x00010004 0x00000045
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0x00010005 0x0000004e
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0x00010006 0x00000057
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0x00010007 0x00000061
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0x00010008 0x0000006b
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0x00010009 0x00000076
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/* Calibration data group 3 */
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0x00020000 0x00000029
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0x00020001 0x00000033
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0x00020002 0x0000003d
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0x00020003 0x00000049
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0x00020004 0x00000056
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0x00020005 0x00000061
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0x00020006 0x0000006d
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/* Calibration data group 4 */
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0x00030000 0x00000021
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0x00030001 0x0000002a
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0x00030002 0x0000003c
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0x00030003 0x0000004e>;
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big-endian;
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#thermal-sensor-cells = <1>;
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};
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thermal-zones {
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cpu_thermal: cpu-thermal {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 3>;
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trips {
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cpu_alert: cpu-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu-crit {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT
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THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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dspi: dspi@2100000 {
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compatible = "fsl,ls1021a-v1.0-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2100000 0x0 0x10000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "dspi";
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clocks = <&clockgen 4 1>;
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spi-num-chipselects = <5>;
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big-endian;
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status = "disabled";
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};
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i2c0: i2c@2180000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2180000 0x0 0x10000>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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dmas = <&edma0 1 39>,
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<&edma0 1 38>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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i2c1: i2c@2190000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2190000 0x0 0x10000>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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status = "disabled";
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};
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i2c2: i2c@21a0000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x21a0000 0x0 0x10000>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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status = "disabled";
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};
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i2c3: i2c@21b0000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x21b0000 0x0 0x10000>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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status = "disabled";
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};
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duart0: serial@21c0500 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x00 0x21c0500 0x0 0x100>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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};
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duart1: serial@21c0600 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x00 0x21c0600 0x0 0x100>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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};
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duart2: serial@21d0500 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21d0500 0x0 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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};
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duart3: serial@21d0600 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21d0600 0x0 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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};
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gpio0: gpio@2300000 {
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compatible = "fsl,qoriq-gpio";
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reg = <0x0 0x2300000 0x0 0x10000>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@2310000 {
|
|
compatible = "fsl,qoriq-gpio";
|
|
reg = <0x0 0x2310000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio@2320000 {
|
|
compatible = "fsl,qoriq-gpio";
|
|
reg = <0x0 0x2320000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio@2330000 {
|
|
compatible = "fsl,qoriq-gpio";
|
|
reg = <0x0 0x2330000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
lpuart0: serial@2950000 {
|
|
compatible = "fsl,ls1021a-lpuart";
|
|
reg = <0x0 0x2950000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 0>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart1: serial@2960000 {
|
|
compatible = "fsl,ls1021a-lpuart";
|
|
reg = <0x0 0x2960000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 1>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart2: serial@2970000 {
|
|
compatible = "fsl,ls1021a-lpuart";
|
|
reg = <0x0 0x2970000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 1>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart3: serial@2980000 {
|
|
compatible = "fsl,ls1021a-lpuart";
|
|
reg = <0x0 0x2980000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 1>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart4: serial@2990000 {
|
|
compatible = "fsl,ls1021a-lpuart";
|
|
reg = <0x0 0x2990000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 1>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart5: serial@29a0000 {
|
|
compatible = "fsl,ls1021a-lpuart";
|
|
reg = <0x0 0x29a0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 1>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
wdog0: watchdog@2ad0000 {
|
|
compatible = "fsl,imx21-wdt";
|
|
reg = <0x0 0x2ad0000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 1>;
|
|
big-endian;
|
|
};
|
|
|
|
edma0: edma@2c00000 {
|
|
#dma-cells = <2>;
|
|
compatible = "fsl,vf610-edma";
|
|
reg = <0x0 0x2c00000 0x0 0x10000>,
|
|
<0x0 0x2c10000 0x0 0x10000>,
|
|
<0x0 0x2c20000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "edma-tx", "edma-err";
|
|
dma-channels = <32>;
|
|
big-endian;
|
|
clock-names = "dmamux0", "dmamux1";
|
|
clocks = <&clockgen 4 1>,
|
|
<&clockgen 4 1>;
|
|
};
|
|
|
|
usb0: usb@2f00000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x0 0x2f00000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
|
dr_mode = "host";
|
|
snps,quirk-frame-length-adjustment = <0x20>;
|
|
snps,dis_rxdet_inp3_quirk;
|
|
};
|
|
|
|
usb1: usb@3000000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x0 0x3000000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
|
dr_mode = "host";
|
|
snps,quirk-frame-length-adjustment = <0x20>;
|
|
snps,dis_rxdet_inp3_quirk;
|
|
};
|
|
|
|
usb2: usb@3100000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x0 0x3100000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
|
dr_mode = "host";
|
|
snps,quirk-frame-length-adjustment = <0x20>;
|
|
snps,dis_rxdet_inp3_quirk;
|
|
};
|
|
|
|
sata: sata@3200000 {
|
|
compatible = "fsl,ls1046a-ahci";
|
|
reg = <0x0 0x3200000 0x0 0x10000>,
|
|
<0x0 0x20140520 0x0 0x4>;
|
|
reg-names = "ahci", "sata-ecc";
|
|
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen 4 1>;
|
|
};
|
|
};
|
|
|
|
reserved-memory {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
bman_fbpr: bman-fbpr {
|
|
compatible = "shared-dma-pool";
|
|
size = <0 0x1000000>;
|
|
alignment = <0 0x1000000>;
|
|
no-map;
|
|
};
|
|
|
|
qman_fqd: qman-fqd {
|
|
compatible = "shared-dma-pool";
|
|
size = <0 0x800000>;
|
|
alignment = <0 0x800000>;
|
|
no-map;
|
|
};
|
|
|
|
qman_pfdr: qman-pfdr {
|
|
compatible = "shared-dma-pool";
|
|
size = <0 0x2000000>;
|
|
alignment = <0 0x2000000>;
|
|
no-map;
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "qoriq-qman-portals.dtsi"
|
|
#include "qoriq-bman-portals.dtsi"
|