forked from Minki/linux
e03f9088e2
Add r8a7779 specific support for IRLM bit configuration in the INTC-IRQPIN driver. Without this code we need special workaround code in arch/arm/mach-shmobile. The IRLM bit for the INTC hardware exists on various older SH-based SoCs and is used to select between two modes for the external interrupt pins IRQ0 to IRQ3: IRLM = 0: (default from reset on r8a7779) In this mode the pins IRQ0 to IRQ3 are used together to give a value between 0 and 15 to the SoC. External logic is required for masking. This mode is not supported by the INTC-IRQPIN driver. IRLM = 1: (needs this patch or configuration elsewhere) In this mode IRQ0 to IRQ3 operate as 4 individual external interrupt pins. In this mode the SMSC ethernet chip can be used via IRQ1 on r8a7779 Marzen. This mode is the only supported mode by the INTC-IRQPIN driver. For this patch to work the r8a7779 DTS needs to pass the ICR0 register as the last register bank. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: horms@verge.net.au Cc: jason@lakedaemon.net Link: http://lkml.kernel.org/r/20141203121803.5936.35881.sendpatchset@w520 Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
28 lines
1.1 KiB
Plaintext
28 lines
1.1 KiB
Plaintext
DT bindings for the R-/SH-Mobile irqpin controller
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Required properties:
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- compatible: has to be "renesas,intc-irqpin-<soctype>", "renesas,intc-irqpin"
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as fallback.
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Examples with soctypes are:
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- "renesas,intc-irqpin-r8a7740" (R-Mobile A1)
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- "renesas,intc-irqpin-r8a7778" (R-Car M1A)
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- "renesas,intc-irqpin-r8a7779" (R-Car H1)
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- "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5)
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- reg: Base address and length of each register bank used by the external
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IRQ pins driven by the interrupt controller hardware module. The base
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addresses, length and number of required register banks varies with soctype.
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- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
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interrupts.txt in this directory
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Optional properties:
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- any properties, listed in interrupts.txt, and any standard resource allocation
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properties
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- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
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if different from the default 4 bits
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- control-parent: disable and enable interrupts on the parent interrupt
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controller, needed for some broken implementations
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