Linus Torvalds 0eff4589c3 It's the usual big pile of driver updates and additions, but we ... do have a couple core changes in here as well. Core: - CLK_IS_CRITICAL support has been added. This should allow drivers to properly express that a certain clk should stay on even if their prepare/enable count drops to 0 (and in turn the parents of these clks should stay enabled). - A clk registration API has been added, clk_hw_register(), and an OF clk provider API has been added, of_clk_add_hw_provider(). These APIs have been put in place to further split clk providers from clk consumers, with the goal being to have clk providers never deal with struct clk pointers at all. Conversion of provider drivers is on going. clkdev has also gained support for registering clk_hw pointers directly so we can convert drivers that don't use devicetree. New Drivers: - Marvell ap806 and cp110 system controllers (with clks inside!) - Hisilicon Hi3519 clock and reset controller - Axis ARTPEC-6 clock controllers - Oxford Semiconductor OXNAS clock controllers - AXS10X I2S PLL - Rockchip RK3399 clock and reset controller Updates: - MMC2 and UART2 clks on Samsung Exynos 3250, ACLK on Samsung Exynos 542x SoCs, and some more clk ID exporting for bus frequency scaling - Proper BCM2835 PCM clk support and various other clks - i.MX clk updates for i.MX6SX, i.MX7, and VF610 - Renesas updates for R-Car H3 - Tegra210 got updates for DisplayPort and HDMI 2.0 - Rockchip driver refactorings and fixes due to adding RK3399 support -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABCAAGBQJXP7QdAAoJEK0CiJfG5JUl/Q8P/i93QXTom/VbwDHZ4DDZr0Hc 69oCRVTDTArGLa4YrGMxu3crNWf8/ORwsZVG93PD6bkkrWo9qH52KFsI22MdZcta HlApsFjI503C7qDw6V8UVz7mUJVfarCxKNSd1WBPCVCNExarIrRRymC3NXT6ZrUP D59E53d4G+I6OUuybsp4gtA7aEoYebAE7BInPDDihIk7Lall5mLYbfJUumpHlmSd wqqPad5OYoC1nkrYhIGficK9Bizy3eyK829EoqpQpE4djkNhEwKd/AwSJZ6i1pdC obt8vQyPRK0ByND2I+3XPqZ7bFb9IKu5WIAkYzG8QskFyIqiFtOkFgEP360ojlGT D8sZY7RBmIM4Tu5RgeoN94wML4f/zYOm6YzVUVjWdVPGoxuy4QhQsvS5Id70ifNU pSYf1KG0Gq0wvptth02zaDE9r1lDMOCHsOPIbVMqHRxRj8shUyjroTEzdtdyS6SE FsYmGdrq4YctXyP4E8efLzFMjN7qZyKgnAoGfROsPRb6NE3DSFs5PcxQldOcoBPv +NstBGUlJ4Xzwd1BdxKWJq8aIsG/CLqTec63OYSYM0bfUSWXKOgemvBV8MJrDP1D rFabdJVHhUZOy5UgxOdfmy1XWp/SWup8OUnpEJp84RywGP6UMM0s1RtWruMJ776J tBzVIIYCJrAWFia0Djlr =aEzb -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "It's the usual big pile of driver updates and additions, but we do have a couple core changes in here as well. Core: - CLK_IS_CRITICAL support has been added. This should allow drivers to properly express that a certain clk should stay on even if their prepare/enable count drops to 0 (and in turn the parents of these clks should stay enabled). - A clk registration API has been added, clk_hw_register(), and an OF clk provider API has been added, of_clk_add_hw_provider(). These APIs have been put in place to further split clk providers from clk consumers, with the goal being to have clk providers never deal with struct clk pointers at all. Conversion of provider drivers is on going. clkdev has also gained support for registering clk_hw pointers directly so we can convert drivers that don't use devicetree. New Drivers: - Marvell ap806 and cp110 system controllers (with clks inside!) - Hisilicon Hi3519 clock and reset controller - Axis ARTPEC-6 clock controllers - Oxford Semiconductor OXNAS clock controllers - AXS10X I2S PLL - Rockchip RK3399 clock and reset controller Updates: - MMC2 and UART2 clks on Samsung Exynos 3250, ACLK on Samsung Exynos 542x SoCs, and some more clk ID exporting for bus frequency scaling - Proper BCM2835 PCM clk support and various other clks - i.MX clk updates for i.MX6SX, i.MX7, and VF610 - Renesas updates for R-Car H3 - Tegra210 got updates for DisplayPort and HDMI 2.0 - Rockchip driver refactorings and fixes due to adding RK3399 support" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (139 commits) clk: fix critical clock locking clk: qcom: mmcc-8996: Remove clocks that should be controlled by RPM clk: ingenic: Allow divider value to be divided clk: sunxi: Add display and TCON0 clocks driver clk: rockchip: drop old_rate calculation on pll rate changes clk: rockchip: simplify GRF handling in pll clocks clk: rockchip: lookup General Register Files in rockchip_clk_init clk: rockchip: fix the rk3399 sdmmc sample / drv name clk: mvebu: new driver for Armada CP110 system controller dt-bindings: arm: add DT binding for Marvell CP110 system controller clk: mvebu: new driver for Armada AP806 system controller clk: hisilicon: add CRG driver for hi3519 soc clk: hisilicon: export some hisilicon APIs to modules reset: hisilicon: add reset controller driver for hisilicon SOCs clk: bcm/kona: Do not use sizeof on pointer type clk: qcom: msm8916: Fix crypto clock flags clk: nxp: lpc18xx: Initialize clk_init_data::flags to 0 clk/axs10x: Add I2S PLL clock driver clk: imx7d: fix ahb clock mux 1 clk: fix comment of devm_clk_hw_register() ...		2016-05-20 20:18:12 -07:00
..
bindings	It's the usual big pile of driver updates and additions, but we	2016-05-20 20:18:12 -07:00
00-INDEX
booting-without-of.txt	sh: add device tree support and generic board using device tree	2016-03-17 19:46:11 +00:00
changesets.txt
dynamic-resolution-notes.txt
of_unittest.txt
overlay-notes.txt
todo.txt
usage-model.txt