forked from Minki/linux
bb58d07964
We are using the smallest padding boundary (8 bytes), which isn't smaller than the Memory Controller Read/Write Size We get best performance in 100G when the Packing Boundary is a multiple of the Maximum Payload Size. Its related to inefficient chopping of DMA packets by PCIe, that causes more overhead on bus. So driver is helping by making the starting address alignment to be MPS size. We will try to determine PCIE MaxPayloadSize capabiltiy and set IngPackBoundary based on this value. If cache line size is greater than MPS or determinig MPS fails, we will use cache line size to determine IngPackBoundary(as before). Signed-off-by: Arjun Vynipadath <arjun@chelsio.com> Signed-off-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
157 lines
5.4 KiB
C
157 lines
5.4 KiB
C
/*
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* This file is part of the Chelsio T4 Ethernet driver for Linux.
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*
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* Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __T4_VALUES_H__
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#define __T4_VALUES_H__
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/* This file contains definitions for various T4 register value hardware
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* constants. The types of values encoded here are predominantly those for
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* register fields which control "modal" behavior. For the most part, we do
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* not include definitions for register fields which are simple numeric
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* metrics, etc.
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*/
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/* SGE register field values.
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*/
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/* CONTROL1 register */
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#define RXPKTCPLMODE_SPLIT_X 1
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#define INGPCIEBOUNDARY_SHIFT_X 5
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#define INGPCIEBOUNDARY_32B_X 0
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#define INGPADBOUNDARY_SHIFT_X 5
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#define T6_INGPADBOUNDARY_SHIFT_X 3
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#define T6_INGPADBOUNDARY_8B_X 0
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#define T6_INGPADBOUNDARY_32B_X 2
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#define INGPADBOUNDARY_32B_X 0
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/* CONTROL2 register */
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#define INGPACKBOUNDARY_SHIFT_X 5
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#define INGPACKBOUNDARY_16B_X 0
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#define INGPACKBOUNDARY_64B_X 1
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/* GTS register */
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#define SGE_TIMERREGS 6
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#define TIMERREG_COUNTER0_X 0
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#define FETCHBURSTMIN_64B_X 2
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#define FETCHBURSTMIN_128B_X 3
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#define FETCHBURSTMAX_256B_X 2
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#define FETCHBURSTMAX_512B_X 3
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#define HOSTFCMODE_STATUS_PAGE_X 2
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#define CIDXFLUSHTHRESH_32_X 5
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#define UPDATEDELIVERY_INTERRUPT_X 1
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#define RSPD_TYPE_FLBUF_X 0
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#define RSPD_TYPE_CPL_X 1
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#define RSPD_TYPE_INTR_X 2
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/* Congestion Manager Definitions.
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*/
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#define CONMCTXT_CNGTPMODE_S 19
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#define CONMCTXT_CNGTPMODE_V(x) ((x) << CONMCTXT_CNGTPMODE_S)
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#define CONMCTXT_CNGCHMAP_S 0
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#define CONMCTXT_CNGCHMAP_V(x) ((x) << CONMCTXT_CNGCHMAP_S)
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#define CONMCTXT_CNGTPMODE_CHANNEL_X 2
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#define CONMCTXT_CNGTPMODE_QUEUE_X 1
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/* T5 and later support a new BAR2-based doorbell mechanism for Egress Queues.
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* The User Doorbells are each 128 bytes in length with a Simple Doorbell at
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* offsets 8x and a Write Combining single 64-byte Egress Queue Unit
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* (IDXSIZE_UNIT_X) Gather Buffer interface at offset 64. For Ingress Queues,
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* we have a Going To Sleep register at offsets 8x+4.
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*
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* As noted above, we have many instances of the Simple Doorbell and Going To
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* Sleep registers at offsets 8x and 8x+4, respectively. We want to use a
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* non-64-byte aligned offset for the Simple Doorbell in order to attempt to
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* avoid buffering of the writes to the Simple Doorbell and we want to use a
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* non-contiguous offset for the Going To Sleep writes in order to avoid
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* possible combining between them.
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*/
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#define SGE_UDB_SIZE 128
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#define SGE_UDB_KDOORBELL 8
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#define SGE_UDB_GTS 20
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#define SGE_UDB_WCDOORBELL 64
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/* CIM register field values.
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*/
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#define X_MBOWNER_FW 1
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#define X_MBOWNER_PL 2
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/* PCI-E definitions */
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#define WINDOW_SHIFT_X 10
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#define PCIEOFST_SHIFT_X 10
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/* TP_VLAN_PRI_MAP controls which subset of fields will be present in the
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* Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP
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* selects for a particular field being present. These fields, when present
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* in the Compressed Filter Tuple, have the following widths in bits.
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*/
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#define FT_FCOE_W 1
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#define FT_PORT_W 3
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#define FT_VNIC_ID_W 17
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#define FT_VLAN_W 17
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#define FT_TOS_W 8
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#define FT_PROTOCOL_W 8
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#define FT_ETHERTYPE_W 16
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#define FT_MACMATCH_W 9
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#define FT_MPSHITTYPE_W 3
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#define FT_FRAGMENTATION_W 1
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/* Some of the Compressed Filter Tuple fields have internal structure. These
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* bit shifts/masks describe those structures. All shifts are relative to the
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* base position of the fields within the Compressed Filter Tuple
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*/
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#define FT_VLAN_VLD_S 16
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#define FT_VLAN_VLD_V(x) ((x) << FT_VLAN_VLD_S)
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#define FT_VLAN_VLD_F FT_VLAN_VLD_V(1U)
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#define FT_VNID_ID_VF_S 0
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#define FT_VNID_ID_VF_V(x) ((x) << FT_VNID_ID_VF_S)
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#define FT_VNID_ID_PF_S 7
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#define FT_VNID_ID_PF_V(x) ((x) << FT_VNID_ID_PF_S)
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#define FT_VNID_ID_VLD_S 16
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#define FT_VNID_ID_VLD_V(x) ((x) << FT_VNID_ID_VLD_S)
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#endif /* __T4_VALUES_H__ */
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