forked from Minki/linux
0eaf4defc7
So far one TCE table could only be used by one IOMMU group. However IODA2 hardware allows programming the same TCE table address to multiple PE allowing sharing tables. This replaces a single pointer to a group in a iommu_table struct with a linked list of groups which provides the way of invalidating TCE cache for every PE when an actual TCE table is updated. This adds pnv_pci_link_table_and_group() and pnv_pci_unlink_table_and_group() helpers to manage the list. However without VFIO, it is still going to be a single IOMMU group per iommu_table. This changes iommu_add_device() to add a device to a first group from the group list of a table as it is only called from the platform init code or PCI bus notifier and at these moments there is only one group per table. This does not change TCE invalidation code to loop through all attached groups in order to simplify this patch and because it is not really needed in most cases. IODA2 is fixed in a later patch. This should cause no behavioural change. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [aw: for the vfio related changes] Acked-by: Alex Williamson <alex.williamson@redhat.com> Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
1171 lines
29 KiB
C
1171 lines
29 KiB
C
/*
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* Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
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*
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* Rewrite, cleanup, new allocation schemes, virtual merging:
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* Copyright (C) 2004 Olof Johansson, IBM Corporation
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* and Ben. Herrenschmidt, IBM Corporation
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*
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* Dynamic DMA mapping support, bus-independent parts.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#include <linux/dma-mapping.h>
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#include <linux/bitmap.h>
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#include <linux/iommu-helper.h>
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#include <linux/crash_dump.h>
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#include <linux/hash.h>
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#include <linux/fault-inject.h>
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#include <linux/pci.h>
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#include <linux/iommu.h>
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#include <linux/sched.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/iommu.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <asm/kdump.h>
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#include <asm/fadump.h>
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#include <asm/vio.h>
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#include <asm/tce.h>
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#define DBG(...)
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static int novmerge;
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static void __iommu_free(struct iommu_table *, dma_addr_t, unsigned int);
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static int __init setup_iommu(char *str)
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{
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if (!strcmp(str, "novmerge"))
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novmerge = 1;
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else if (!strcmp(str, "vmerge"))
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novmerge = 0;
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return 1;
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}
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__setup("iommu=", setup_iommu);
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static DEFINE_PER_CPU(unsigned int, iommu_pool_hash);
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/*
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* We precalculate the hash to avoid doing it on every allocation.
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*
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* The hash is important to spread CPUs across all the pools. For example,
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* on a POWER7 with 4 way SMT we want interrupts on the primary threads and
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* with 4 pools all primary threads would map to the same pool.
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*/
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static int __init setup_iommu_pool_hash(void)
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{
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unsigned int i;
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for_each_possible_cpu(i)
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per_cpu(iommu_pool_hash, i) = hash_32(i, IOMMU_POOL_HASHBITS);
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return 0;
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}
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subsys_initcall(setup_iommu_pool_hash);
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#ifdef CONFIG_FAIL_IOMMU
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static DECLARE_FAULT_ATTR(fail_iommu);
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static int __init setup_fail_iommu(char *str)
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{
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return setup_fault_attr(&fail_iommu, str);
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}
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__setup("fail_iommu=", setup_fail_iommu);
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static bool should_fail_iommu(struct device *dev)
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{
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return dev->archdata.fail_iommu && should_fail(&fail_iommu, 1);
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}
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static int __init fail_iommu_debugfs(void)
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{
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struct dentry *dir = fault_create_debugfs_attr("fail_iommu",
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NULL, &fail_iommu);
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return PTR_ERR_OR_ZERO(dir);
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}
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late_initcall(fail_iommu_debugfs);
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static ssize_t fail_iommu_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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return sprintf(buf, "%d\n", dev->archdata.fail_iommu);
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}
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static ssize_t fail_iommu_store(struct device *dev,
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struct device_attribute *attr, const char *buf,
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size_t count)
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{
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int i;
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if (count > 0 && sscanf(buf, "%d", &i) > 0)
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dev->archdata.fail_iommu = (i == 0) ? 0 : 1;
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return count;
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}
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static DEVICE_ATTR(fail_iommu, S_IRUGO|S_IWUSR, fail_iommu_show,
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fail_iommu_store);
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static int fail_iommu_bus_notify(struct notifier_block *nb,
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unsigned long action, void *data)
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{
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struct device *dev = data;
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if (action == BUS_NOTIFY_ADD_DEVICE) {
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if (device_create_file(dev, &dev_attr_fail_iommu))
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pr_warn("Unable to create IOMMU fault injection sysfs "
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"entries\n");
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} else if (action == BUS_NOTIFY_DEL_DEVICE) {
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device_remove_file(dev, &dev_attr_fail_iommu);
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}
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return 0;
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}
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static struct notifier_block fail_iommu_bus_notifier = {
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.notifier_call = fail_iommu_bus_notify
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};
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static int __init fail_iommu_setup(void)
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{
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#ifdef CONFIG_PCI
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bus_register_notifier(&pci_bus_type, &fail_iommu_bus_notifier);
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#endif
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#ifdef CONFIG_IBMVIO
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bus_register_notifier(&vio_bus_type, &fail_iommu_bus_notifier);
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#endif
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return 0;
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}
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/*
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* Must execute after PCI and VIO subsystem have initialised but before
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* devices are probed.
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*/
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arch_initcall(fail_iommu_setup);
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#else
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static inline bool should_fail_iommu(struct device *dev)
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{
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return false;
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}
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#endif
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static unsigned long iommu_range_alloc(struct device *dev,
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struct iommu_table *tbl,
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unsigned long npages,
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unsigned long *handle,
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unsigned long mask,
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unsigned int align_order)
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{
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unsigned long n, end, start;
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unsigned long limit;
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int largealloc = npages > 15;
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int pass = 0;
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unsigned long align_mask;
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unsigned long boundary_size;
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unsigned long flags;
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unsigned int pool_nr;
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struct iommu_pool *pool;
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align_mask = 0xffffffffffffffffl >> (64 - align_order);
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/* This allocator was derived from x86_64's bit string search */
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/* Sanity check */
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if (unlikely(npages == 0)) {
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if (printk_ratelimit())
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WARN_ON(1);
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return DMA_ERROR_CODE;
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}
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if (should_fail_iommu(dev))
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return DMA_ERROR_CODE;
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/*
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* We don't need to disable preemption here because any CPU can
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* safely use any IOMMU pool.
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*/
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pool_nr = __this_cpu_read(iommu_pool_hash) & (tbl->nr_pools - 1);
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if (largealloc)
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pool = &(tbl->large_pool);
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else
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pool = &(tbl->pools[pool_nr]);
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spin_lock_irqsave(&(pool->lock), flags);
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again:
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if ((pass == 0) && handle && *handle &&
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(*handle >= pool->start) && (*handle < pool->end))
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start = *handle;
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else
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start = pool->hint;
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limit = pool->end;
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/* The case below can happen if we have a small segment appended
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* to a large, or when the previous alloc was at the very end of
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* the available space. If so, go back to the initial start.
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*/
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if (start >= limit)
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start = pool->start;
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if (limit + tbl->it_offset > mask) {
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limit = mask - tbl->it_offset + 1;
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/* If we're constrained on address range, first try
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* at the masked hint to avoid O(n) search complexity,
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* but on second pass, start at 0 in pool 0.
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*/
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if ((start & mask) >= limit || pass > 0) {
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spin_unlock(&(pool->lock));
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pool = &(tbl->pools[0]);
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spin_lock(&(pool->lock));
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start = pool->start;
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} else {
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start &= mask;
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}
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}
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if (dev)
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boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
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1 << tbl->it_page_shift);
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else
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boundary_size = ALIGN(1UL << 32, 1 << tbl->it_page_shift);
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/* 4GB boundary for iseries_hv_alloc and iseries_hv_map */
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n = iommu_area_alloc(tbl->it_map, limit, start, npages, tbl->it_offset,
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boundary_size >> tbl->it_page_shift, align_mask);
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if (n == -1) {
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if (likely(pass == 0)) {
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/* First try the pool from the start */
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pool->hint = pool->start;
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pass++;
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goto again;
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} else if (pass <= tbl->nr_pools) {
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/* Now try scanning all the other pools */
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spin_unlock(&(pool->lock));
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pool_nr = (pool_nr + 1) & (tbl->nr_pools - 1);
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pool = &tbl->pools[pool_nr];
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spin_lock(&(pool->lock));
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pool->hint = pool->start;
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pass++;
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goto again;
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} else {
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/* Give up */
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spin_unlock_irqrestore(&(pool->lock), flags);
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return DMA_ERROR_CODE;
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}
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}
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end = n + npages;
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/* Bump the hint to a new block for small allocs. */
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if (largealloc) {
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/* Don't bump to new block to avoid fragmentation */
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pool->hint = end;
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} else {
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/* Overflow will be taken care of at the next allocation */
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pool->hint = (end + tbl->it_blocksize - 1) &
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~(tbl->it_blocksize - 1);
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}
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/* Update handle for SG allocations */
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if (handle)
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*handle = end;
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spin_unlock_irqrestore(&(pool->lock), flags);
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return n;
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}
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static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
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void *page, unsigned int npages,
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enum dma_data_direction direction,
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unsigned long mask, unsigned int align_order,
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struct dma_attrs *attrs)
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{
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unsigned long entry;
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dma_addr_t ret = DMA_ERROR_CODE;
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int build_fail;
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entry = iommu_range_alloc(dev, tbl, npages, NULL, mask, align_order);
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if (unlikely(entry == DMA_ERROR_CODE))
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return DMA_ERROR_CODE;
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entry += tbl->it_offset; /* Offset into real TCE table */
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ret = entry << tbl->it_page_shift; /* Set the return dma address */
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/* Put the TCEs in the HW table */
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build_fail = tbl->it_ops->set(tbl, entry, npages,
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(unsigned long)page &
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IOMMU_PAGE_MASK(tbl), direction, attrs);
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/* tbl->it_ops->set() only returns non-zero for transient errors.
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* Clean up the table bitmap in this case and return
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* DMA_ERROR_CODE. For all other errors the functionality is
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* not altered.
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*/
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if (unlikely(build_fail)) {
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__iommu_free(tbl, ret, npages);
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return DMA_ERROR_CODE;
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}
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/* Flush/invalidate TLB caches if necessary */
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if (tbl->it_ops->flush)
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tbl->it_ops->flush(tbl);
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/* Make sure updates are seen by hardware */
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mb();
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return ret;
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}
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static bool iommu_free_check(struct iommu_table *tbl, dma_addr_t dma_addr,
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unsigned int npages)
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{
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unsigned long entry, free_entry;
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entry = dma_addr >> tbl->it_page_shift;
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free_entry = entry - tbl->it_offset;
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if (((free_entry + npages) > tbl->it_size) ||
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(entry < tbl->it_offset)) {
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if (printk_ratelimit()) {
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printk(KERN_INFO "iommu_free: invalid entry\n");
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printk(KERN_INFO "\tentry = 0x%lx\n", entry);
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printk(KERN_INFO "\tdma_addr = 0x%llx\n", (u64)dma_addr);
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printk(KERN_INFO "\tTable = 0x%llx\n", (u64)tbl);
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printk(KERN_INFO "\tbus# = 0x%llx\n", (u64)tbl->it_busno);
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printk(KERN_INFO "\tsize = 0x%llx\n", (u64)tbl->it_size);
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printk(KERN_INFO "\tstartOff = 0x%llx\n", (u64)tbl->it_offset);
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printk(KERN_INFO "\tindex = 0x%llx\n", (u64)tbl->it_index);
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WARN_ON(1);
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}
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return false;
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}
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return true;
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}
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static struct iommu_pool *get_pool(struct iommu_table *tbl,
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unsigned long entry)
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{
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struct iommu_pool *p;
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unsigned long largepool_start = tbl->large_pool.start;
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/* The large pool is the last pool at the top of the table */
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if (entry >= largepool_start) {
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p = &tbl->large_pool;
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} else {
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unsigned int pool_nr = entry / tbl->poolsize;
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BUG_ON(pool_nr > tbl->nr_pools);
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p = &tbl->pools[pool_nr];
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}
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return p;
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}
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static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
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unsigned int npages)
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{
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unsigned long entry, free_entry;
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unsigned long flags;
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struct iommu_pool *pool;
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entry = dma_addr >> tbl->it_page_shift;
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free_entry = entry - tbl->it_offset;
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pool = get_pool(tbl, free_entry);
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if (!iommu_free_check(tbl, dma_addr, npages))
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return;
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tbl->it_ops->clear(tbl, entry, npages);
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spin_lock_irqsave(&(pool->lock), flags);
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bitmap_clear(tbl->it_map, free_entry, npages);
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spin_unlock_irqrestore(&(pool->lock), flags);
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}
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static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
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unsigned int npages)
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{
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__iommu_free(tbl, dma_addr, npages);
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|
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/* Make sure TLB cache is flushed if the HW needs it. We do
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* not do an mb() here on purpose, it is not needed on any of
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* the current platforms.
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*/
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if (tbl->it_ops->flush)
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tbl->it_ops->flush(tbl);
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}
|
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|
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int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl,
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struct scatterlist *sglist, int nelems,
|
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unsigned long mask, enum dma_data_direction direction,
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struct dma_attrs *attrs)
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{
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dma_addr_t dma_next = 0, dma_addr;
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struct scatterlist *s, *outs, *segstart;
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int outcount, incount, i, build_fail = 0;
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unsigned int align;
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unsigned long handle;
|
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unsigned int max_seg_size;
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|
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BUG_ON(direction == DMA_NONE);
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|
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if ((nelems == 0) || !tbl)
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return 0;
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outs = s = segstart = &sglist[0];
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outcount = 1;
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incount = nelems;
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handle = 0;
|
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|
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/* Init first segment length for backout at failure */
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outs->dma_length = 0;
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|
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DBG("sg mapping %d elements:\n", nelems);
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|
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max_seg_size = dma_get_max_seg_size(dev);
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for_each_sg(sglist, s, nelems, i) {
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unsigned long vaddr, npages, entry, slen;
|
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|
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slen = s->length;
|
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/* Sanity check */
|
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if (slen == 0) {
|
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dma_next = 0;
|
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continue;
|
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}
|
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/* Allocate iommu entries for that segment */
|
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vaddr = (unsigned long) sg_virt(s);
|
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npages = iommu_num_pages(vaddr, slen, IOMMU_PAGE_SIZE(tbl));
|
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align = 0;
|
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if (tbl->it_page_shift < PAGE_SHIFT && slen >= PAGE_SIZE &&
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(vaddr & ~PAGE_MASK) == 0)
|
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align = PAGE_SHIFT - tbl->it_page_shift;
|
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entry = iommu_range_alloc(dev, tbl, npages, &handle,
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mask >> tbl->it_page_shift, align);
|
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|
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DBG(" - vaddr: %lx, size: %lx\n", vaddr, slen);
|
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|
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/* Handle failure */
|
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if (unlikely(entry == DMA_ERROR_CODE)) {
|
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if (printk_ratelimit())
|
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dev_info(dev, "iommu_alloc failed, tbl %p "
|
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"vaddr %lx npages %lu\n", tbl, vaddr,
|
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npages);
|
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goto failure;
|
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}
|
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|
|
/* Convert entry to a dma_addr_t */
|
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entry += tbl->it_offset;
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dma_addr = entry << tbl->it_page_shift;
|
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dma_addr |= (s->offset & ~IOMMU_PAGE_MASK(tbl));
|
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|
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DBG(" - %lu pages, entry: %lx, dma_addr: %lx\n",
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npages, entry, dma_addr);
|
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|
|
/* Insert into HW table */
|
|
build_fail = tbl->it_ops->set(tbl, entry, npages,
|
|
vaddr & IOMMU_PAGE_MASK(tbl),
|
|
direction, attrs);
|
|
if(unlikely(build_fail))
|
|
goto failure;
|
|
|
|
/* If we are in an open segment, try merging */
|
|
if (segstart != s) {
|
|
DBG(" - trying merge...\n");
|
|
/* We cannot merge if:
|
|
* - allocated dma_addr isn't contiguous to previous allocation
|
|
*/
|
|
if (novmerge || (dma_addr != dma_next) ||
|
|
(outs->dma_length + s->length > max_seg_size)) {
|
|
/* Can't merge: create a new segment */
|
|
segstart = s;
|
|
outcount++;
|
|
outs = sg_next(outs);
|
|
DBG(" can't merge, new segment.\n");
|
|
} else {
|
|
outs->dma_length += s->length;
|
|
DBG(" merged, new len: %ux\n", outs->dma_length);
|
|
}
|
|
}
|
|
|
|
if (segstart == s) {
|
|
/* This is a new segment, fill entries */
|
|
DBG(" - filling new segment.\n");
|
|
outs->dma_address = dma_addr;
|
|
outs->dma_length = slen;
|
|
}
|
|
|
|
/* Calculate next page pointer for contiguous check */
|
|
dma_next = dma_addr + slen;
|
|
|
|
DBG(" - dma next is: %lx\n", dma_next);
|
|
}
|
|
|
|
/* Flush/invalidate TLB caches if necessary */
|
|
if (tbl->it_ops->flush)
|
|
tbl->it_ops->flush(tbl);
|
|
|
|
DBG("mapped %d elements:\n", outcount);
|
|
|
|
/* For the sake of ppc_iommu_unmap_sg, we clear out the length in the
|
|
* next entry of the sglist if we didn't fill the list completely
|
|
*/
|
|
if (outcount < incount) {
|
|
outs = sg_next(outs);
|
|
outs->dma_address = DMA_ERROR_CODE;
|
|
outs->dma_length = 0;
|
|
}
|
|
|
|
/* Make sure updates are seen by hardware */
|
|
mb();
|
|
|
|
return outcount;
|
|
|
|
failure:
|
|
for_each_sg(sglist, s, nelems, i) {
|
|
if (s->dma_length != 0) {
|
|
unsigned long vaddr, npages;
|
|
|
|
vaddr = s->dma_address & IOMMU_PAGE_MASK(tbl);
|
|
npages = iommu_num_pages(s->dma_address, s->dma_length,
|
|
IOMMU_PAGE_SIZE(tbl));
|
|
__iommu_free(tbl, vaddr, npages);
|
|
s->dma_address = DMA_ERROR_CODE;
|
|
s->dma_length = 0;
|
|
}
|
|
if (s == outs)
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
void ppc_iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
|
|
int nelems, enum dma_data_direction direction,
|
|
struct dma_attrs *attrs)
|
|
{
|
|
struct scatterlist *sg;
|
|
|
|
BUG_ON(direction == DMA_NONE);
|
|
|
|
if (!tbl)
|
|
return;
|
|
|
|
sg = sglist;
|
|
while (nelems--) {
|
|
unsigned int npages;
|
|
dma_addr_t dma_handle = sg->dma_address;
|
|
|
|
if (sg->dma_length == 0)
|
|
break;
|
|
npages = iommu_num_pages(dma_handle, sg->dma_length,
|
|
IOMMU_PAGE_SIZE(tbl));
|
|
__iommu_free(tbl, dma_handle, npages);
|
|
sg = sg_next(sg);
|
|
}
|
|
|
|
/* Flush/invalidate TLBs if necessary. As for iommu_free(), we
|
|
* do not do an mb() here, the affected platforms do not need it
|
|
* when freeing.
|
|
*/
|
|
if (tbl->it_ops->flush)
|
|
tbl->it_ops->flush(tbl);
|
|
}
|
|
|
|
static void iommu_table_clear(struct iommu_table *tbl)
|
|
{
|
|
/*
|
|
* In case of firmware assisted dump system goes through clean
|
|
* reboot process at the time of system crash. Hence it's safe to
|
|
* clear the TCE entries if firmware assisted dump is active.
|
|
*/
|
|
if (!is_kdump_kernel() || is_fadump_active()) {
|
|
/* Clear the table in case firmware left allocations in it */
|
|
tbl->it_ops->clear(tbl, tbl->it_offset, tbl->it_size);
|
|
return;
|
|
}
|
|
|
|
#ifdef CONFIG_CRASH_DUMP
|
|
if (tbl->it_ops->get) {
|
|
unsigned long index, tceval, tcecount = 0;
|
|
|
|
/* Reserve the existing mappings left by the first kernel. */
|
|
for (index = 0; index < tbl->it_size; index++) {
|
|
tceval = tbl->it_ops->get(tbl, index + tbl->it_offset);
|
|
/*
|
|
* Freed TCE entry contains 0x7fffffffffffffff on JS20
|
|
*/
|
|
if (tceval && (tceval != 0x7fffffffffffffffUL)) {
|
|
__set_bit(index, tbl->it_map);
|
|
tcecount++;
|
|
}
|
|
}
|
|
|
|
if ((tbl->it_size - tcecount) < KDUMP_MIN_TCE_ENTRIES) {
|
|
printk(KERN_WARNING "TCE table is full; freeing ");
|
|
printk(KERN_WARNING "%d entries for the kdump boot\n",
|
|
KDUMP_MIN_TCE_ENTRIES);
|
|
for (index = tbl->it_size - KDUMP_MIN_TCE_ENTRIES;
|
|
index < tbl->it_size; index++)
|
|
__clear_bit(index, tbl->it_map);
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Build a iommu_table structure. This contains a bit map which
|
|
* is used to manage allocation of the tce space.
|
|
*/
|
|
struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid)
|
|
{
|
|
unsigned long sz;
|
|
static int welcomed = 0;
|
|
struct page *page;
|
|
unsigned int i;
|
|
struct iommu_pool *p;
|
|
|
|
BUG_ON(!tbl->it_ops);
|
|
|
|
/* number of bytes needed for the bitmap */
|
|
sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long);
|
|
|
|
page = alloc_pages_node(nid, GFP_KERNEL, get_order(sz));
|
|
if (!page)
|
|
panic("iommu_init_table: Can't allocate %ld bytes\n", sz);
|
|
tbl->it_map = page_address(page);
|
|
memset(tbl->it_map, 0, sz);
|
|
|
|
/*
|
|
* Reserve page 0 so it will not be used for any mappings.
|
|
* This avoids buggy drivers that consider page 0 to be invalid
|
|
* to crash the machine or even lose data.
|
|
*/
|
|
if (tbl->it_offset == 0)
|
|
set_bit(0, tbl->it_map);
|
|
|
|
/* We only split the IOMMU table if we have 1GB or more of space */
|
|
if ((tbl->it_size << tbl->it_page_shift) >= (1UL * 1024 * 1024 * 1024))
|
|
tbl->nr_pools = IOMMU_NR_POOLS;
|
|
else
|
|
tbl->nr_pools = 1;
|
|
|
|
/* We reserve the top 1/4 of the table for large allocations */
|
|
tbl->poolsize = (tbl->it_size * 3 / 4) / tbl->nr_pools;
|
|
|
|
for (i = 0; i < tbl->nr_pools; i++) {
|
|
p = &tbl->pools[i];
|
|
spin_lock_init(&(p->lock));
|
|
p->start = tbl->poolsize * i;
|
|
p->hint = p->start;
|
|
p->end = p->start + tbl->poolsize;
|
|
}
|
|
|
|
p = &tbl->large_pool;
|
|
spin_lock_init(&(p->lock));
|
|
p->start = tbl->poolsize * i;
|
|
p->hint = p->start;
|
|
p->end = tbl->it_size;
|
|
|
|
iommu_table_clear(tbl);
|
|
|
|
if (!welcomed) {
|
|
printk(KERN_INFO "IOMMU table initialized, virtual merging %s\n",
|
|
novmerge ? "disabled" : "enabled");
|
|
welcomed = 1;
|
|
}
|
|
|
|
return tbl;
|
|
}
|
|
|
|
void iommu_free_table(struct iommu_table *tbl, const char *node_name)
|
|
{
|
|
unsigned long bitmap_sz;
|
|
unsigned int order;
|
|
|
|
if (!tbl)
|
|
return;
|
|
|
|
if (!tbl->it_map) {
|
|
kfree(tbl);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* In case we have reserved the first bit, we should not emit
|
|
* the warning below.
|
|
*/
|
|
if (tbl->it_offset == 0)
|
|
clear_bit(0, tbl->it_map);
|
|
|
|
/* verify that table contains no entries */
|
|
if (!bitmap_empty(tbl->it_map, tbl->it_size))
|
|
pr_warn("%s: Unexpected TCEs for %s\n", __func__, node_name);
|
|
|
|
/* calculate bitmap size in bytes */
|
|
bitmap_sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long);
|
|
|
|
/* free bitmap */
|
|
order = get_order(bitmap_sz);
|
|
free_pages((unsigned long) tbl->it_map, order);
|
|
|
|
/* free table */
|
|
kfree(tbl);
|
|
}
|
|
|
|
/* Creates TCEs for a user provided buffer. The user buffer must be
|
|
* contiguous real kernel storage (not vmalloc). The address passed here
|
|
* comprises a page address and offset into that page. The dma_addr_t
|
|
* returned will point to the same byte within the page as was passed in.
|
|
*/
|
|
dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl,
|
|
struct page *page, unsigned long offset, size_t size,
|
|
unsigned long mask, enum dma_data_direction direction,
|
|
struct dma_attrs *attrs)
|
|
{
|
|
dma_addr_t dma_handle = DMA_ERROR_CODE;
|
|
void *vaddr;
|
|
unsigned long uaddr;
|
|
unsigned int npages, align;
|
|
|
|
BUG_ON(direction == DMA_NONE);
|
|
|
|
vaddr = page_address(page) + offset;
|
|
uaddr = (unsigned long)vaddr;
|
|
npages = iommu_num_pages(uaddr, size, IOMMU_PAGE_SIZE(tbl));
|
|
|
|
if (tbl) {
|
|
align = 0;
|
|
if (tbl->it_page_shift < PAGE_SHIFT && size >= PAGE_SIZE &&
|
|
((unsigned long)vaddr & ~PAGE_MASK) == 0)
|
|
align = PAGE_SHIFT - tbl->it_page_shift;
|
|
|
|
dma_handle = iommu_alloc(dev, tbl, vaddr, npages, direction,
|
|
mask >> tbl->it_page_shift, align,
|
|
attrs);
|
|
if (dma_handle == DMA_ERROR_CODE) {
|
|
if (printk_ratelimit()) {
|
|
dev_info(dev, "iommu_alloc failed, tbl %p "
|
|
"vaddr %p npages %d\n", tbl, vaddr,
|
|
npages);
|
|
}
|
|
} else
|
|
dma_handle |= (uaddr & ~IOMMU_PAGE_MASK(tbl));
|
|
}
|
|
|
|
return dma_handle;
|
|
}
|
|
|
|
void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
|
|
size_t size, enum dma_data_direction direction,
|
|
struct dma_attrs *attrs)
|
|
{
|
|
unsigned int npages;
|
|
|
|
BUG_ON(direction == DMA_NONE);
|
|
|
|
if (tbl) {
|
|
npages = iommu_num_pages(dma_handle, size,
|
|
IOMMU_PAGE_SIZE(tbl));
|
|
iommu_free(tbl, dma_handle, npages);
|
|
}
|
|
}
|
|
|
|
/* Allocates a contiguous real buffer and creates mappings over it.
|
|
* Returns the virtual address of the buffer and sets dma_handle
|
|
* to the dma address (mapping) of the first page.
|
|
*/
|
|
void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
|
|
size_t size, dma_addr_t *dma_handle,
|
|
unsigned long mask, gfp_t flag, int node)
|
|
{
|
|
void *ret = NULL;
|
|
dma_addr_t mapping;
|
|
unsigned int order;
|
|
unsigned int nio_pages, io_order;
|
|
struct page *page;
|
|
|
|
size = PAGE_ALIGN(size);
|
|
order = get_order(size);
|
|
|
|
/*
|
|
* Client asked for way too much space. This is checked later
|
|
* anyway. It is easier to debug here for the drivers than in
|
|
* the tce tables.
|
|
*/
|
|
if (order >= IOMAP_MAX_ORDER) {
|
|
dev_info(dev, "iommu_alloc_consistent size too large: 0x%lx\n",
|
|
size);
|
|
return NULL;
|
|
}
|
|
|
|
if (!tbl)
|
|
return NULL;
|
|
|
|
/* Alloc enough pages (and possibly more) */
|
|
page = alloc_pages_node(node, flag, order);
|
|
if (!page)
|
|
return NULL;
|
|
ret = page_address(page);
|
|
memset(ret, 0, size);
|
|
|
|
/* Set up tces to cover the allocated range */
|
|
nio_pages = size >> tbl->it_page_shift;
|
|
io_order = get_iommu_order(size, tbl);
|
|
mapping = iommu_alloc(dev, tbl, ret, nio_pages, DMA_BIDIRECTIONAL,
|
|
mask >> tbl->it_page_shift, io_order, NULL);
|
|
if (mapping == DMA_ERROR_CODE) {
|
|
free_pages((unsigned long)ret, order);
|
|
return NULL;
|
|
}
|
|
*dma_handle = mapping;
|
|
return ret;
|
|
}
|
|
|
|
void iommu_free_coherent(struct iommu_table *tbl, size_t size,
|
|
void *vaddr, dma_addr_t dma_handle)
|
|
{
|
|
if (tbl) {
|
|
unsigned int nio_pages;
|
|
|
|
size = PAGE_ALIGN(size);
|
|
nio_pages = size >> tbl->it_page_shift;
|
|
iommu_free(tbl, dma_handle, nio_pages);
|
|
size = PAGE_ALIGN(size);
|
|
free_pages((unsigned long)vaddr, get_order(size));
|
|
}
|
|
}
|
|
|
|
unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir)
|
|
{
|
|
switch (dir) {
|
|
case DMA_BIDIRECTIONAL:
|
|
return TCE_PCI_READ | TCE_PCI_WRITE;
|
|
case DMA_FROM_DEVICE:
|
|
return TCE_PCI_WRITE;
|
|
case DMA_TO_DEVICE:
|
|
return TCE_PCI_READ;
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
EXPORT_SYMBOL_GPL(iommu_direction_to_tce_perm);
|
|
|
|
#ifdef CONFIG_IOMMU_API
|
|
/*
|
|
* SPAPR TCE API
|
|
*/
|
|
static void group_release(void *iommu_data)
|
|
{
|
|
struct iommu_table_group *table_group = iommu_data;
|
|
|
|
table_group->group = NULL;
|
|
}
|
|
|
|
void iommu_register_group(struct iommu_table_group *table_group,
|
|
int pci_domain_number, unsigned long pe_num)
|
|
{
|
|
struct iommu_group *grp;
|
|
char *name;
|
|
|
|
grp = iommu_group_alloc();
|
|
if (IS_ERR(grp)) {
|
|
pr_warn("powerpc iommu api: cannot create new group, err=%ld\n",
|
|
PTR_ERR(grp));
|
|
return;
|
|
}
|
|
table_group->group = grp;
|
|
iommu_group_set_iommudata(grp, table_group, group_release);
|
|
name = kasprintf(GFP_KERNEL, "domain%d-pe%lx",
|
|
pci_domain_number, pe_num);
|
|
if (!name)
|
|
return;
|
|
iommu_group_set_name(grp, name);
|
|
kfree(name);
|
|
}
|
|
|
|
enum dma_data_direction iommu_tce_direction(unsigned long tce)
|
|
{
|
|
if ((tce & TCE_PCI_READ) && (tce & TCE_PCI_WRITE))
|
|
return DMA_BIDIRECTIONAL;
|
|
else if (tce & TCE_PCI_READ)
|
|
return DMA_TO_DEVICE;
|
|
else if (tce & TCE_PCI_WRITE)
|
|
return DMA_FROM_DEVICE;
|
|
else
|
|
return DMA_NONE;
|
|
}
|
|
EXPORT_SYMBOL_GPL(iommu_tce_direction);
|
|
|
|
void iommu_flush_tce(struct iommu_table *tbl)
|
|
{
|
|
/* Flush/invalidate TLB caches if necessary */
|
|
if (tbl->it_ops->flush)
|
|
tbl->it_ops->flush(tbl);
|
|
|
|
/* Make sure updates are seen by hardware */
|
|
mb();
|
|
}
|
|
EXPORT_SYMBOL_GPL(iommu_flush_tce);
|
|
|
|
int iommu_tce_clear_param_check(struct iommu_table *tbl,
|
|
unsigned long ioba, unsigned long tce_value,
|
|
unsigned long npages)
|
|
{
|
|
/* tbl->it_ops->clear() does not support any value but 0 */
|
|
if (tce_value)
|
|
return -EINVAL;
|
|
|
|
if (ioba & ~IOMMU_PAGE_MASK(tbl))
|
|
return -EINVAL;
|
|
|
|
ioba >>= tbl->it_page_shift;
|
|
if (ioba < tbl->it_offset)
|
|
return -EINVAL;
|
|
|
|
if ((ioba + npages) > (tbl->it_offset + tbl->it_size))
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(iommu_tce_clear_param_check);
|
|
|
|
int iommu_tce_put_param_check(struct iommu_table *tbl,
|
|
unsigned long ioba, unsigned long tce)
|
|
{
|
|
if (!(tce & (TCE_PCI_WRITE | TCE_PCI_READ)))
|
|
return -EINVAL;
|
|
|
|
if (tce & ~(IOMMU_PAGE_MASK(tbl) | TCE_PCI_WRITE | TCE_PCI_READ))
|
|
return -EINVAL;
|
|
|
|
if (ioba & ~IOMMU_PAGE_MASK(tbl))
|
|
return -EINVAL;
|
|
|
|
ioba >>= tbl->it_page_shift;
|
|
if (ioba < tbl->it_offset)
|
|
return -EINVAL;
|
|
|
|
if ((ioba + 1) > (tbl->it_offset + tbl->it_size))
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(iommu_tce_put_param_check);
|
|
|
|
unsigned long iommu_clear_tce(struct iommu_table *tbl, unsigned long entry)
|
|
{
|
|
unsigned long oldtce;
|
|
struct iommu_pool *pool = get_pool(tbl, entry);
|
|
|
|
spin_lock(&(pool->lock));
|
|
|
|
oldtce = tbl->it_ops->get(tbl, entry);
|
|
if (oldtce & (TCE_PCI_WRITE | TCE_PCI_READ))
|
|
tbl->it_ops->clear(tbl, entry, 1);
|
|
else
|
|
oldtce = 0;
|
|
|
|
spin_unlock(&(pool->lock));
|
|
|
|
return oldtce;
|
|
}
|
|
EXPORT_SYMBOL_GPL(iommu_clear_tce);
|
|
|
|
/*
|
|
* hwaddr is a kernel virtual address here (0xc... bazillion),
|
|
* tce_build converts it to a physical address.
|
|
*/
|
|
int iommu_tce_build(struct iommu_table *tbl, unsigned long entry,
|
|
unsigned long hwaddr, enum dma_data_direction direction)
|
|
{
|
|
int ret = -EBUSY;
|
|
unsigned long oldtce;
|
|
struct iommu_pool *pool = get_pool(tbl, entry);
|
|
|
|
spin_lock(&(pool->lock));
|
|
|
|
oldtce = tbl->it_ops->get(tbl, entry);
|
|
/* Add new entry if it is not busy */
|
|
if (!(oldtce & (TCE_PCI_WRITE | TCE_PCI_READ)))
|
|
ret = tbl->it_ops->set(tbl, entry, 1, hwaddr, direction, NULL);
|
|
|
|
spin_unlock(&(pool->lock));
|
|
|
|
/* if (unlikely(ret))
|
|
pr_err("iommu_tce: %s failed on hwaddr=%lx ioba=%lx kva=%lx ret=%d\n",
|
|
__func__, hwaddr, entry << tbl->it_page_shift,
|
|
hwaddr, ret); */
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(iommu_tce_build);
|
|
|
|
int iommu_take_ownership(struct iommu_table *tbl)
|
|
{
|
|
unsigned long sz = (tbl->it_size + 7) >> 3;
|
|
|
|
if (tbl->it_offset == 0)
|
|
clear_bit(0, tbl->it_map);
|
|
|
|
if (!bitmap_empty(tbl->it_map, tbl->it_size)) {
|
|
pr_err("iommu_tce: it_map is not empty");
|
|
return -EBUSY;
|
|
}
|
|
|
|
memset(tbl->it_map, 0xff, sz);
|
|
|
|
/*
|
|
* Disable iommu bypass, otherwise the user can DMA to all of
|
|
* our physical memory via the bypass window instead of just
|
|
* the pages that has been explicitly mapped into the iommu
|
|
*/
|
|
if (tbl->set_bypass)
|
|
tbl->set_bypass(tbl, false);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(iommu_take_ownership);
|
|
|
|
void iommu_release_ownership(struct iommu_table *tbl)
|
|
{
|
|
unsigned long sz = (tbl->it_size + 7) >> 3;
|
|
|
|
memset(tbl->it_map, 0, sz);
|
|
|
|
/* Restore bit#0 set by iommu_init_table() */
|
|
if (tbl->it_offset == 0)
|
|
set_bit(0, tbl->it_map);
|
|
|
|
/* The kernel owns the device now, we can restore the iommu bypass */
|
|
if (tbl->set_bypass)
|
|
tbl->set_bypass(tbl, true);
|
|
}
|
|
EXPORT_SYMBOL_GPL(iommu_release_ownership);
|
|
|
|
int iommu_add_device(struct device *dev)
|
|
{
|
|
struct iommu_table *tbl;
|
|
struct iommu_table_group_link *tgl;
|
|
|
|
/*
|
|
* The sysfs entries should be populated before
|
|
* binding IOMMU group. If sysfs entries isn't
|
|
* ready, we simply bail.
|
|
*/
|
|
if (!device_is_registered(dev))
|
|
return -ENOENT;
|
|
|
|
if (dev->iommu_group) {
|
|
pr_debug("%s: Skipping device %s with iommu group %d\n",
|
|
__func__, dev_name(dev),
|
|
iommu_group_id(dev->iommu_group));
|
|
return -EBUSY;
|
|
}
|
|
|
|
tbl = get_iommu_table_base(dev);
|
|
if (!tbl) {
|
|
pr_debug("%s: Skipping device %s with no tbl\n",
|
|
__func__, dev_name(dev));
|
|
return 0;
|
|
}
|
|
|
|
tgl = list_first_entry_or_null(&tbl->it_group_list,
|
|
struct iommu_table_group_link, next);
|
|
if (!tgl) {
|
|
pr_debug("%s: Skipping device %s with no group\n",
|
|
__func__, dev_name(dev));
|
|
return 0;
|
|
}
|
|
pr_debug("%s: Adding %s to iommu group %d\n",
|
|
__func__, dev_name(dev),
|
|
iommu_group_id(tgl->table_group->group));
|
|
|
|
if (PAGE_SIZE < IOMMU_PAGE_SIZE(tbl)) {
|
|
pr_err("%s: Invalid IOMMU page size %lx (%lx) on %s\n",
|
|
__func__, IOMMU_PAGE_SIZE(tbl),
|
|
PAGE_SIZE, dev_name(dev));
|
|
return -EINVAL;
|
|
}
|
|
|
|
return iommu_group_add_device(tgl->table_group->group, dev);
|
|
}
|
|
EXPORT_SYMBOL_GPL(iommu_add_device);
|
|
|
|
void iommu_del_device(struct device *dev)
|
|
{
|
|
/*
|
|
* Some devices might not have IOMMU table and group
|
|
* and we needn't detach them from the associated
|
|
* IOMMU groups
|
|
*/
|
|
if (!dev->iommu_group) {
|
|
pr_debug("iommu_tce: skipping device %s with no tbl\n",
|
|
dev_name(dev));
|
|
return;
|
|
}
|
|
|
|
iommu_group_remove_device(dev);
|
|
}
|
|
EXPORT_SYMBOL_GPL(iommu_del_device);
|
|
|
|
static int tce_iommu_bus_notifier(struct notifier_block *nb,
|
|
unsigned long action, void *data)
|
|
{
|
|
struct device *dev = data;
|
|
|
|
switch (action) {
|
|
case BUS_NOTIFY_ADD_DEVICE:
|
|
return iommu_add_device(dev);
|
|
case BUS_NOTIFY_DEL_DEVICE:
|
|
if (dev->iommu_group)
|
|
iommu_del_device(dev);
|
|
return 0;
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static struct notifier_block tce_iommu_bus_nb = {
|
|
.notifier_call = tce_iommu_bus_notifier,
|
|
};
|
|
|
|
int __init tce_iommu_bus_notifier_init(void)
|
|
{
|
|
bus_register_notifier(&pci_bus_type, &tce_iommu_bus_nb);
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_IOMMU_API */
|