forked from Minki/linux
a1d2a63399
- Mali 4xx GPUs have two kinds of processors GP and PP. GP is for OpenGL vertex shader processing and PP is for fragment shader processing. Each processor has its own MMU so prcessors work in virtual address space. - There's only one GP but multiple PP (max 4 for mali 400 and 8 for mali 450) in the same mali 4xx GPU. All PPs are grouped togather to handle a single fragment shader task divided by FB output tiled pixels. Mali 400 user space driver is responsible for assign target tiled pixels to each PP, but mali 450 has a HW module called DLBU to dynamically balance each PP's load. - User space driver allocate buffer object and map into GPU virtual address space, upload command stream and draw data with CPU mmap of the buffer object, then submit task to GP/PP with a register frame indicating where is the command stream and misc settings. - There's no command stream validation/relocation due to each user process has its own GPU virtual address space. GP/PP's MMU switch virtual address space before running two tasks from different user process. Error or evil user space code just get MMU fault or GP/PP error IRQ, then the HW/SW will be recovered. - Use GEM+shmem for MM. Currently just alloc and pin memory when gem object creation. GPU vm map of the buffer is also done in the alloc stage in kernel space. We may delay the memory allocation and real GPU vm map to command submission stage in the furture as improvement. - Use drm_sched for GPU task schedule. Each OpenGL context should have a lima context object in the kernel to distinguish tasks from different user. drm_sched gets task from each lima context in a fair way. mesa driver can be found here before upstreamed: https://gitlab.freedesktop.org/lima/mesa v8: - add comments for in_sync - fix ctx free miss mutex unlock v7: - remove lima_fence_ops with default value - move fence slab create to device probe - check pad ioctl args to be zero - add comments for user/kernel interface v6: - fix comments by checkpatch.pl v5: - export gp/pp version to userspace - rebase on drm-misc-next v4: - use get param interface to get info - separate context create/free ioctl - remove unused max sched task param - update copyright time - use xarray instead of idr - stop using drmP.h v3: - fix comments from kbuild robot - restrict supported arch to tested ones v2: - fix syscall argument check - fix job finish fence leak since kernel 5.0 - use drm syncobj to replace native fence - move buffer object GPU va map into kernel - reserve syscall argument space for future info - remove kernel gem modifier - switch TTM back to GEM+shmem MM - use time based io poll - use whole register name - adopt gem reservation obj integration - use drm_timeout_abs_to_jiffies Cc: Eric Anholt <eric@anholt.net> Cc: Rob Herring <robh@kernel.org> Cc: Christian König <ckoenig.leichtzumerken@gmail.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Alex Deucher <alexdeucher@gmail.com> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Rob Clark <robdclark@gmail.com> Cc: Dave Airlie <airlied@gmail.com> Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de> Signed-off-by: Erico Nunes <nunes.erico@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Simon Shields <simon@lineageos.org> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Rob Herring <robh@kerrnel.org> Signed-off-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/291200/
170 lines
4.7 KiB
C
170 lines
4.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR MIT */
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/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
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#ifndef __LIMA_DRM_H__
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#define __LIMA_DRM_H__
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#include "drm.h"
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#if defined(__cplusplus)
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extern "C" {
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#endif
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enum drm_lima_param_gpu_id {
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DRM_LIMA_PARAM_GPU_ID_UNKNOWN,
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DRM_LIMA_PARAM_GPU_ID_MALI400,
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DRM_LIMA_PARAM_GPU_ID_MALI450,
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};
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enum drm_lima_param {
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DRM_LIMA_PARAM_GPU_ID,
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DRM_LIMA_PARAM_NUM_PP,
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DRM_LIMA_PARAM_GP_VERSION,
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DRM_LIMA_PARAM_PP_VERSION,
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};
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/**
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* get various information of the GPU
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*/
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struct drm_lima_get_param {
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__u32 param; /* in, value in enum drm_lima_param */
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__u32 pad; /* pad, must be zero */
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__u64 value; /* out, parameter value */
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};
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/**
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* create a buffer for used by GPU
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*/
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struct drm_lima_gem_create {
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__u32 size; /* in, buffer size */
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__u32 flags; /* in, currently no flags, must be zero */
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__u32 handle; /* out, GEM buffer handle */
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__u32 pad; /* pad, must be zero */
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};
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/**
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* get information of a buffer
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*/
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struct drm_lima_gem_info {
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__u32 handle; /* in, GEM buffer handle */
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__u32 va; /* out, virtual address mapped into GPU MMU */
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__u64 offset; /* out, used to mmap this buffer to CPU */
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};
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#define LIMA_SUBMIT_BO_READ 0x01
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#define LIMA_SUBMIT_BO_WRITE 0x02
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/* buffer information used by one task */
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struct drm_lima_gem_submit_bo {
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__u32 handle; /* in, GEM buffer handle */
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__u32 flags; /* in, buffer read/write by GPU */
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};
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#define LIMA_GP_FRAME_REG_NUM 6
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/* frame used to setup GP for each task */
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struct drm_lima_gp_frame {
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__u32 frame[LIMA_GP_FRAME_REG_NUM];
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};
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#define LIMA_PP_FRAME_REG_NUM 23
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#define LIMA_PP_WB_REG_NUM 12
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/* frame used to setup mali400 GPU PP for each task */
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struct drm_lima_m400_pp_frame {
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__u32 frame[LIMA_PP_FRAME_REG_NUM];
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__u32 num_pp;
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__u32 wb[3 * LIMA_PP_WB_REG_NUM];
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__u32 plbu_array_address[4];
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__u32 fragment_stack_address[4];
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};
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/* frame used to setup mali450 GPU PP for each task */
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struct drm_lima_m450_pp_frame {
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__u32 frame[LIMA_PP_FRAME_REG_NUM];
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__u32 num_pp;
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__u32 wb[3 * LIMA_PP_WB_REG_NUM];
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__u32 use_dlbu;
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__u32 _pad;
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union {
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__u32 plbu_array_address[8];
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__u32 dlbu_regs[4];
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};
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__u32 fragment_stack_address[8];
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};
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#define LIMA_PIPE_GP 0x00
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#define LIMA_PIPE_PP 0x01
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#define LIMA_SUBMIT_FLAG_EXPLICIT_FENCE (1 << 0)
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/**
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* submit a task to GPU
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*
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* User can always merge multi sync_file and drm_syncobj
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* into one drm_syncobj as in_sync[0], but we reserve
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* in_sync[1] for another task's out_sync to avoid the
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* export/import/merge pass when explicit sync.
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*/
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struct drm_lima_gem_submit {
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__u32 ctx; /* in, context handle task is submitted to */
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__u32 pipe; /* in, which pipe to use, GP/PP */
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__u32 nr_bos; /* in, array length of bos field */
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__u32 frame_size; /* in, size of frame field */
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__u64 bos; /* in, array of drm_lima_gem_submit_bo */
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__u64 frame; /* in, GP/PP frame */
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__u32 flags; /* in, submit flags */
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__u32 out_sync; /* in, drm_syncobj handle used to wait task finish after submission */
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__u32 in_sync[2]; /* in, drm_syncobj handle used to wait before start this task */
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};
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#define LIMA_GEM_WAIT_READ 0x01
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#define LIMA_GEM_WAIT_WRITE 0x02
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/**
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* wait pending GPU task finish of a buffer
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*/
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struct drm_lima_gem_wait {
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__u32 handle; /* in, GEM buffer handle */
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__u32 op; /* in, CPU want to read/write this buffer */
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__s64 timeout_ns; /* in, wait timeout in absulute time */
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};
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/**
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* create a context
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*/
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struct drm_lima_ctx_create {
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__u32 id; /* out, context handle */
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__u32 _pad; /* pad, must be zero */
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};
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/**
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* free a context
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*/
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struct drm_lima_ctx_free {
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__u32 id; /* in, context handle */
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__u32 _pad; /* pad, must be zero */
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};
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#define DRM_LIMA_GET_PARAM 0x00
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#define DRM_LIMA_GEM_CREATE 0x01
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#define DRM_LIMA_GEM_INFO 0x02
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#define DRM_LIMA_GEM_SUBMIT 0x03
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#define DRM_LIMA_GEM_WAIT 0x04
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#define DRM_LIMA_CTX_CREATE 0x05
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#define DRM_LIMA_CTX_FREE 0x06
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#define DRM_IOCTL_LIMA_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GET_PARAM, struct drm_lima_get_param)
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#define DRM_IOCTL_LIMA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_CREATE, struct drm_lima_gem_create)
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#define DRM_IOCTL_LIMA_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_INFO, struct drm_lima_gem_info)
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#define DRM_IOCTL_LIMA_GEM_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_SUBMIT, struct drm_lima_gem_submit)
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#define DRM_IOCTL_LIMA_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_WAIT, struct drm_lima_gem_wait)
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#define DRM_IOCTL_LIMA_CTX_CREATE DRM_IOR(DRM_COMMAND_BASE + DRM_LIMA_CTX_CREATE, struct drm_lima_ctx_create)
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#define DRM_IOCTL_LIMA_CTX_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_CTX_FREE, struct drm_lima_ctx_free)
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __LIMA_DRM_H__ */
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