09206b600c
The power9_idle_stop method currently takes only the requested stop level as a parameter and picks up the rest of the PSSCR bits from a hand-coded macro. This is not a very flexible design, especially when the firmware has the capability to communicate the psscr value and the mask associated with a particular stop state via device tree. This patch modifies the power9_idle_stop API to take as parameters the PSSCR value and the PSSCR mask corresponding to the stop state that needs to be set. These PSSCR value and mask are respectively obtained by parsing the "ibm,cpu-idle-state-psscr" and "ibm,cpu-idle-state-psscr-mask" fields from the device tree. In addition to this, the patch adds support for handling stop states for which ESL and EC bits in the PSSCR are zero. As per the architecture, a wakeup from these stop states resumes execution from the subsequent instruction as opposed to waking up at the System Vector. The older firmware sets only the Requested Level (RL) field in the psscr and psscr-mask exposed in the device tree. For older firmware where psscr-mask=0xf, this patch will set the default sane values that the set for for remaining PSSCR fields (i.e PSLL, MTL, ESL, EC, and TR). For the new firmware, the patch will validate that the invariants required by the ISA for the psscr values are maintained by the firmware. This skiboot patch that exports fully populated PSSCR values and the mask for all the stop states can be found here: https://lists.ozlabs.org/pipermail/skiboot/2016-September/004869.html [Optimize the number of instructions before entering STOP with ESL=EC=0, validate the PSSCR values provided by the firimware maintains the invariants required as per the ISA suggested by Balbir Singh] Acked-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
32 lines
664 B
C
32 lines
664 B
C
#ifndef _POWERNV_H
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#define _POWERNV_H
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#ifdef CONFIG_SMP
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extern void pnv_smp_init(void);
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#else
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static inline void pnv_smp_init(void) { }
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#endif
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struct pci_dev;
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#ifdef CONFIG_PCI
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extern void pnv_pci_init(void);
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extern void pnv_pci_shutdown(void);
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#else
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static inline void pnv_pci_init(void) { }
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static inline void pnv_pci_shutdown(void) { }
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#endif
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extern u32 pnv_get_supported_cpuidle_states(void);
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extern u64 pnv_deepest_stop_psscr_val;
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extern u64 pnv_deepest_stop_psscr_mask;
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extern void pnv_lpc_init(void);
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extern void opal_handle_events(uint64_t events);
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extern void opal_event_shutdown(void);
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bool cpu_core_split_required(void);
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#endif /* _POWERNV_H */
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