forked from Minki/linux
911800765e
GuC and HuC depend on struct_mutex for device reinitialization. Moving
away from this dependency requires perma-pinning the firmware images in
GGTT. The upper portion of the GuC address space has a sizeable hole
(several MB) that is inaccessible by GuC. Reserve this range within GGTT
as it can comfortably hold GuC/HuC firmware images.
v2: Reserve node rather than insert (Chris)
Simpler determination of node start/size (Daniele)
Move reserve/release out to intel_guc.* files
v3: Reserve starting at GUC_GGTT_TOP only and bail if this
fails (Chris)
Signed-off-by: Fernando Pacheco <fernando.pacheco@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190419230015.18121-3-fernando.pacheco@intel.com
203 lines
6.4 KiB
C
203 lines
6.4 KiB
C
/*
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* Copyright © 2014-2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#ifndef _INTEL_GUC_H_
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#define _INTEL_GUC_H_
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#include "intel_uncore.h"
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#include "intel_guc_fw.h"
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#include "intel_guc_fwif.h"
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#include "intel_guc_ct.h"
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#include "intel_guc_log.h"
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#include "intel_guc_reg.h"
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#include "intel_uc_fw.h"
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#include "i915_utils.h"
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#include "i915_vma.h"
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struct guc_preempt_work {
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struct work_struct work;
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struct intel_engine_cs *engine;
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};
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/*
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* Top level structure of GuC. It handles firmware loading and manages client
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* pool and doorbells. intel_guc owns a intel_guc_client to replace the legacy
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* ExecList submission.
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*/
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struct intel_guc {
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struct intel_uc_fw fw;
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struct intel_guc_log log;
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struct intel_guc_ct ct;
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/* Log snapshot if GuC errors during load */
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struct drm_i915_gem_object *load_err_log;
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/* intel_guc_recv interrupt related state */
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spinlock_t irq_lock;
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bool interrupts_enabled;
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unsigned int msg_enabled_mask;
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struct i915_vma *ads_vma;
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struct i915_vma *stage_desc_pool;
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void *stage_desc_pool_vaddr;
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struct ida stage_ids;
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struct i915_vma *shared_data;
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void *shared_data_vaddr;
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struct intel_guc_client *execbuf_client;
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struct intel_guc_client *preempt_client;
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struct guc_preempt_work preempt_work[I915_NUM_ENGINES];
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struct workqueue_struct *preempt_wq;
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DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
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/* Cyclic counter mod pagesize */
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u32 db_cacheline;
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/* GuC's FW specific registers used in MMIO send */
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struct {
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u32 base;
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unsigned int count;
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enum forcewake_domains fw_domains;
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} send_regs;
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/* To serialize the intel_guc_send actions */
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struct mutex send_mutex;
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/* GuC's FW specific send function */
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int (*send)(struct intel_guc *guc, const u32 *data, u32 len,
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u32 *response_buf, u32 response_buf_size);
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/* GuC's FW specific event handler function */
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void (*handler)(struct intel_guc *guc);
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/* GuC's FW specific notify function */
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void (*notify)(struct intel_guc *guc);
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};
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static inline bool intel_guc_is_alive(struct intel_guc *guc)
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{
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return intel_uc_fw_is_loaded(&guc->fw);
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}
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static
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inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
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{
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return guc->send(guc, action, len, NULL, 0);
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}
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static inline int
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intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len,
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u32 *response_buf, u32 response_buf_size)
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{
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return guc->send(guc, action, len, response_buf, response_buf_size);
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}
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static inline void intel_guc_notify(struct intel_guc *guc)
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{
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guc->notify(guc);
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}
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static inline void intel_guc_to_host_event_handler(struct intel_guc *guc)
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{
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guc->handler(guc);
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}
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/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
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#define GUC_GGTT_TOP 0xFEE00000
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/**
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* intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma
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* @guc: intel_guc structure.
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* @vma: i915 graphics virtual memory area.
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*
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* GuC does not allow any gfx GGTT address that falls into range
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* [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
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* Currently, in order to exclude [0, ggtt.pin_bias) address space from
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* GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma()
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* and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.
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*
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* Return: GGTT offset of the @vma.
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*/
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static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
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struct i915_vma *vma)
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{
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u32 offset = i915_ggtt_offset(vma);
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GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma));
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GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
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return offset;
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}
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void intel_guc_init_early(struct intel_guc *guc);
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void intel_guc_init_send_regs(struct intel_guc *guc);
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void intel_guc_init_params(struct intel_guc *guc);
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int intel_guc_init_misc(struct intel_guc *guc);
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int intel_guc_init(struct intel_guc *guc);
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void intel_guc_fini(struct intel_guc *guc);
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void intel_guc_fini_misc(struct intel_guc *guc);
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int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
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u32 *response_buf, u32 response_buf_size);
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int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
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u32 *response_buf, u32 response_buf_size);
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void intel_guc_to_host_event_handler(struct intel_guc *guc);
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void intel_guc_to_host_event_handler_nop(struct intel_guc *guc);
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void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc);
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int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
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const u32 *payload, u32 len);
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int intel_guc_sample_forcewake(struct intel_guc *guc);
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int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
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int intel_guc_suspend(struct intel_guc *guc);
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int intel_guc_resume(struct intel_guc *guc);
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struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
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u32 intel_guc_reserved_gtt_size(struct intel_guc *guc);
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int intel_guc_reserve_ggtt_top(struct intel_guc *guc);
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void intel_guc_release_ggtt_top(struct intel_guc *guc);
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static inline int intel_guc_sanitize(struct intel_guc *guc)
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{
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intel_uc_fw_sanitize(&guc->fw);
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return 0;
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}
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static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask)
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{
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spin_lock_irq(&guc->irq_lock);
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guc->msg_enabled_mask |= mask;
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spin_unlock_irq(&guc->irq_lock);
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}
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static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask)
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{
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spin_lock_irq(&guc->irq_lock);
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guc->msg_enabled_mask &= ~mask;
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spin_unlock_irq(&guc->irq_lock);
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}
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int intel_guc_reset_engine(struct intel_guc *guc,
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struct intel_engine_cs *engine);
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#endif
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