forked from Minki/linux
144213d71c
There is no good reason for the asymmetry in the parameters of eth_port_uc_addr_get() and eth_port_uc_addr_set(). Make them symmetric. Remove some gratuitous block comments while we're here. Signed-off-by: Gabriel Paubert <paubert@iram.es> Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
367 lines
11 KiB
C
367 lines
11 KiB
C
#ifndef __MV643XX_ETH_H__
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#define __MV643XX_ETH_H__
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/workqueue.h>
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#include <linux/mii.h>
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#include <linux/mv643xx.h>
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#include <asm/dma-mapping.h>
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/* Checksum offload for Tx works for most packets, but
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* fails if previous packet sent did not use hw csum
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*/
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#define MV643XX_CHECKSUM_OFFLOAD_TX
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#define MV643XX_NAPI
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#define MV643XX_TX_FAST_REFILL
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#undef MV643XX_COAL
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/*
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* Number of RX / TX descriptors on RX / TX rings.
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* Note that allocating RX descriptors is done by allocating the RX
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* ring AND a preallocated RX buffers (skb's) for each descriptor.
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* The TX descriptors only allocates the TX descriptors ring,
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* with no pre allocated TX buffers (skb's are allocated by higher layers.
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*/
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/* Default TX ring size is 1000 descriptors */
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#define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
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/* Default RX ring size is 400 descriptors */
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#define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
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#define MV643XX_TX_COAL 100
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#ifdef MV643XX_COAL
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#define MV643XX_RX_COAL 100
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#endif
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#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
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#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
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#else
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#define MAX_DESCS_PER_SKB 1
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#endif
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#define ETH_VLAN_HLEN 4
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#define ETH_FCS_LEN 4
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#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
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#define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
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ETH_VLAN_HLEN + ETH_FCS_LEN)
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#define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + dma_get_cache_alignment())
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#define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
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#define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
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#define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
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#define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
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#define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
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#define ETH_INT_CAUSE_EXT 0x00000002
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#define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
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#define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
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#define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
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#define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
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#define ETH_INT_CAUSE_PHY 0x00010000
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#define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY)
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#define ETH_INT_MASK_ALL 0x00000000
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#define ETH_INT_MASK_ALL_EXT 0x00000000
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#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
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#define PHY_WAIT_MICRO_SECONDS 10
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/* Buffer offset from buffer pointer */
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#define RX_BUF_OFFSET 0x2
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/* Gigabit Ethernet Unit Global Registers */
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/* MIB Counters register definitions */
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#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
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#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
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#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
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#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
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#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
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#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
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#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
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#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
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#define ETH_MIB_FRAMES_64_OCTETS 0x20
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#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
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#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
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#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
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#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
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#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
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#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
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#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
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#define ETH_MIB_GOOD_FRAMES_SENT 0x40
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#define ETH_MIB_EXCESSIVE_COLLISION 0x44
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#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
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#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
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#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
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#define ETH_MIB_FC_SENT 0x54
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#define ETH_MIB_GOOD_FC_RECEIVED 0x58
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#define ETH_MIB_BAD_FC_RECEIVED 0x5c
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#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
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#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
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#define ETH_MIB_OVERSIZE_RECEIVED 0x68
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#define ETH_MIB_JABBER_RECEIVED 0x6c
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#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
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#define ETH_MIB_BAD_CRC_EVENT 0x74
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#define ETH_MIB_COLLISION 0x78
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#define ETH_MIB_LATE_COLLISION 0x7c
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/* Port serial status reg (PSR) */
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#define ETH_INTERFACE_PCM 0x00000001
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#define ETH_LINK_IS_UP 0x00000002
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#define ETH_PORT_AT_FULL_DUPLEX 0x00000004
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#define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
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#define ETH_GMII_SPEED_1000 0x00000010
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#define ETH_MII_SPEED_100 0x00000020
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#define ETH_TX_IN_PROGRESS 0x00000080
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#define ETH_BYPASS_ACTIVE 0x00000100
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#define ETH_PORT_AT_PARTITION_STATE 0x00000200
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#define ETH_PORT_TX_FIFO_EMPTY 0x00000400
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/* SMI reg */
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#define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
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#define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
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#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
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#define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
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/* Interrupt Cause Register Bit Definitions */
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/* SDMA command status fields macros */
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/* Tx & Rx descriptors status */
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#define ETH_ERROR_SUMMARY 0x00000001
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/* Tx & Rx descriptors command */
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#define ETH_BUFFER_OWNED_BY_DMA 0x80000000
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/* Tx descriptors status */
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#define ETH_LC_ERROR 0
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#define ETH_UR_ERROR 0x00000002
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#define ETH_RL_ERROR 0x00000004
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#define ETH_LLC_SNAP_FORMAT 0x00000200
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/* Rx descriptors status */
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#define ETH_OVERRUN_ERROR 0x00000002
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#define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
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#define ETH_RESOURCE_ERROR 0x00000006
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#define ETH_VLAN_TAGGED 0x00080000
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#define ETH_BPDU_FRAME 0x00100000
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#define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
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#define ETH_OTHER_FRAME_TYPE 0x00400000
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#define ETH_LAYER_2_IS_ETH_V_2 0x00800000
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#define ETH_FRAME_TYPE_IP_V_4 0x01000000
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#define ETH_FRAME_HEADER_OK 0x02000000
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#define ETH_RX_LAST_DESC 0x04000000
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#define ETH_RX_FIRST_DESC 0x08000000
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#define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
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#define ETH_RX_ENABLE_INTERRUPT 0x20000000
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#define ETH_LAYER_4_CHECKSUM_OK 0x40000000
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/* Rx descriptors byte count */
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#define ETH_FRAME_FRAGMENTED 0x00000004
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/* Tx descriptors command */
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#define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
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#define ETH_FRAME_SET_TO_VLAN 0x00008000
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#define ETH_UDP_FRAME 0x00010000
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#define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
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#define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
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#define ETH_ZERO_PADDING 0x00080000
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#define ETH_TX_LAST_DESC 0x00100000
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#define ETH_TX_FIRST_DESC 0x00200000
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#define ETH_GEN_CRC 0x00400000
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#define ETH_TX_ENABLE_INTERRUPT 0x00800000
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#define ETH_AUTO_MODE 0x40000000
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#define ETH_TX_IHL_SHIFT 11
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/* typedefs */
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typedef enum _eth_func_ret_status {
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ETH_OK, /* Returned as expected. */
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ETH_ERROR, /* Fundamental error. */
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ETH_RETRY, /* Could not process request. Try later.*/
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ETH_END_OF_JOB, /* Ring has nothing to process. */
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ETH_QUEUE_FULL, /* Ring resource error. */
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ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
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} ETH_FUNC_RET_STATUS;
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typedef enum _eth_target {
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ETH_TARGET_DRAM,
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ETH_TARGET_DEVICE,
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ETH_TARGET_CBS,
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ETH_TARGET_PCI0,
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ETH_TARGET_PCI1
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} ETH_TARGET;
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/* These are for big-endian machines. Little endian needs different
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* definitions.
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*/
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#if defined(__BIG_ENDIAN)
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struct eth_rx_desc {
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u16 byte_cnt; /* Descriptor buffer byte count */
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u16 buf_size; /* Buffer size */
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u32 cmd_sts; /* Descriptor command status */
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u32 next_desc_ptr; /* Next descriptor pointer */
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u32 buf_ptr; /* Descriptor buffer pointer */
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};
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struct eth_tx_desc {
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u16 byte_cnt; /* buffer byte count */
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u16 l4i_chk; /* CPU provided TCP checksum */
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u32 cmd_sts; /* Command/status field */
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u32 next_desc_ptr; /* Pointer to next descriptor */
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u32 buf_ptr; /* pointer to buffer for this descriptor*/
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};
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#elif defined(__LITTLE_ENDIAN)
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struct eth_rx_desc {
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u32 cmd_sts; /* Descriptor command status */
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u16 buf_size; /* Buffer size */
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u16 byte_cnt; /* Descriptor buffer byte count */
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u32 buf_ptr; /* Descriptor buffer pointer */
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u32 next_desc_ptr; /* Next descriptor pointer */
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};
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struct eth_tx_desc {
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u32 cmd_sts; /* Command/status field */
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u16 l4i_chk; /* CPU provided TCP checksum */
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u16 byte_cnt; /* buffer byte count */
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u32 buf_ptr; /* pointer to buffer for this descriptor*/
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u32 next_desc_ptr; /* Pointer to next descriptor */
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};
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#else
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#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
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#endif
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/* Unified struct for Rx and Tx operations. The user is not required to */
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/* be familier with neither Tx nor Rx descriptors. */
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struct pkt_info {
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unsigned short byte_cnt; /* Descriptor buffer byte count */
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unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
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unsigned int cmd_sts; /* Descriptor command status */
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dma_addr_t buf_ptr; /* Descriptor buffer pointer */
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struct sk_buff *return_info; /* User resource return information */
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};
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/* Ethernet port specific information */
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struct mv643xx_mib_counters {
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u64 good_octets_received;
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u32 bad_octets_received;
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u32 internal_mac_transmit_err;
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u32 good_frames_received;
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u32 bad_frames_received;
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u32 broadcast_frames_received;
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u32 multicast_frames_received;
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u32 frames_64_octets;
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u32 frames_65_to_127_octets;
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u32 frames_128_to_255_octets;
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u32 frames_256_to_511_octets;
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u32 frames_512_to_1023_octets;
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u32 frames_1024_to_max_octets;
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u64 good_octets_sent;
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u32 good_frames_sent;
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u32 excessive_collision;
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u32 multicast_frames_sent;
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u32 broadcast_frames_sent;
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u32 unrec_mac_control_received;
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u32 fc_sent;
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u32 good_fc_received;
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u32 bad_fc_received;
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u32 undersize_received;
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u32 fragments_received;
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u32 oversize_received;
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u32 jabber_received;
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u32 mac_receive_error;
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u32 bad_crc_event;
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u32 collision;
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u32 late_collision;
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};
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struct mv643xx_private {
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int port_num; /* User Ethernet port number */
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u32 rx_sram_addr; /* Base address of rx sram area */
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u32 rx_sram_size; /* Size of rx sram area */
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u32 tx_sram_addr; /* Base address of tx sram area */
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u32 tx_sram_size; /* Size of tx sram area */
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int rx_resource_err; /* Rx ring resource error flag */
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/* Tx/Rx rings managment indexes fields. For driver use */
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/* Next available and first returning Rx resource */
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int rx_curr_desc_q, rx_used_desc_q;
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/* Next available and first returning Tx resource */
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int tx_curr_desc_q, tx_used_desc_q;
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#ifdef MV643XX_TX_FAST_REFILL
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u32 tx_clean_threshold;
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#endif
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struct eth_rx_desc *p_rx_desc_area;
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dma_addr_t rx_desc_dma;
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int rx_desc_area_size;
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struct sk_buff **rx_skb;
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struct eth_tx_desc *p_tx_desc_area;
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dma_addr_t tx_desc_dma;
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int tx_desc_area_size;
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struct sk_buff **tx_skb;
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struct work_struct tx_timeout_task;
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struct net_device_stats stats;
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struct mv643xx_mib_counters mib_counters;
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spinlock_t lock;
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/* Size of Tx Ring per queue */
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int tx_ring_size;
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/* Number of tx descriptors in use */
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int tx_desc_count;
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/* Size of Rx Ring per queue */
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int rx_ring_size;
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/* Number of rx descriptors in use */
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int rx_desc_count;
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/*
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* Used in case RX Ring is empty, which can be caused when
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* system does not have resources (skb's)
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*/
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struct timer_list timeout;
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u32 rx_int_coal;
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u32 tx_int_coal;
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struct mii_if_info mii;
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};
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/* Port operation control routines */
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static void eth_port_init(struct mv643xx_private *mp);
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static void eth_port_reset(unsigned int eth_port_num);
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static void eth_port_start(struct net_device *dev);
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/* PHY and MIB routines */
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static void ethernet_phy_reset(unsigned int eth_port_num);
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static void eth_port_write_smi_reg(unsigned int eth_port_num,
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unsigned int phy_reg, unsigned int value);
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static void eth_port_read_smi_reg(unsigned int eth_port_num,
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unsigned int phy_reg, unsigned int *value);
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static void eth_clear_mib_counters(unsigned int eth_port_num);
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/* Port data flow control routines */
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static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
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struct pkt_info *p_pkt_info);
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static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
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struct pkt_info *p_pkt_info);
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#endif /* __MV643XX_ETH_H__ */
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