forked from Minki/linux
c530bb8a72
The mbi_lock mutex is left uninitialized, so let's use DEFINE_MUTEX
to initialize it statically.
Fixes: 505287525c
("irqchip/gic-v3: Add support for Message Based Interrupts as an MSI controller")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
332 lines
7.9 KiB
C
332 lines
7.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 ARM Limited, All Rights Reserved.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#define pr_fmt(fmt) "GICv3: " fmt
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#include <linux/dma-iommu.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/msi.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/irqchip/arm-gic-v3.h>
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struct mbi_range {
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u32 spi_start;
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u32 nr_spis;
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unsigned long *bm;
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};
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static DEFINE_MUTEX(mbi_lock);
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static phys_addr_t mbi_phys_base;
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static struct mbi_range *mbi_ranges;
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static unsigned int mbi_range_nr;
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static struct irq_chip mbi_irq_chip = {
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.name = "MBI",
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_set_type = irq_chip_set_type_parent,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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};
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static int mbi_irq_gic_domain_alloc(struct irq_domain *domain,
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unsigned int virq,
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irq_hw_number_t hwirq)
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{
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struct irq_fwspec fwspec;
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struct irq_data *d;
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int err;
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/*
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* Using ACPI? There is no MBI support in the spec, you
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* shouldn't even be here.
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*/
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if (!is_of_node(domain->parent->fwnode))
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return -EINVAL;
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/*
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* Let's default to edge. This is consistent with traditional
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* MSIs, and systems requiring level signaling will just
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* enforce the trigger on their own.
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*/
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fwspec.fwnode = domain->parent->fwnode;
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fwspec.param_count = 3;
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fwspec.param[0] = 0;
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fwspec.param[1] = hwirq - 32;
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fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
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err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
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if (err)
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return err;
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d = irq_domain_get_irq_data(domain->parent, virq);
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return d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
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}
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static void mbi_free_msi(struct mbi_range *mbi, unsigned int hwirq,
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int nr_irqs)
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{
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mutex_lock(&mbi_lock);
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bitmap_release_region(mbi->bm, hwirq - mbi->spi_start,
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get_count_order(nr_irqs));
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mutex_unlock(&mbi_lock);
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}
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static int mbi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *args)
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{
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struct mbi_range *mbi = NULL;
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int hwirq, offset, i, err = 0;
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mutex_lock(&mbi_lock);
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for (i = 0; i < mbi_range_nr; i++) {
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offset = bitmap_find_free_region(mbi_ranges[i].bm,
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mbi_ranges[i].nr_spis,
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get_count_order(nr_irqs));
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if (offset >= 0) {
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mbi = &mbi_ranges[i];
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break;
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}
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}
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mutex_unlock(&mbi_lock);
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if (!mbi)
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return -ENOSPC;
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hwirq = mbi->spi_start + offset;
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for (i = 0; i < nr_irqs; i++) {
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err = mbi_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
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if (err)
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goto fail;
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irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
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&mbi_irq_chip, mbi);
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}
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return 0;
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fail:
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irq_domain_free_irqs_parent(domain, virq, nr_irqs);
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mbi_free_msi(mbi, hwirq, nr_irqs);
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return err;
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}
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static void mbi_irq_domain_free(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
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{
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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struct mbi_range *mbi = irq_data_get_irq_chip_data(d);
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mbi_free_msi(mbi, d->hwirq, nr_irqs);
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irq_domain_free_irqs_parent(domain, virq, nr_irqs);
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}
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static const struct irq_domain_ops mbi_domain_ops = {
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.alloc = mbi_irq_domain_alloc,
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.free = mbi_irq_domain_free,
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};
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static void mbi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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{
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msg[0].address_hi = upper_32_bits(mbi_phys_base + GICD_SETSPI_NSR);
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msg[0].address_lo = lower_32_bits(mbi_phys_base + GICD_SETSPI_NSR);
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msg[0].data = data->parent_data->hwirq;
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iommu_dma_map_msi_msg(data->irq, msg);
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}
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#ifdef CONFIG_PCI_MSI
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/* PCI-specific irqchip */
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static void mbi_mask_msi_irq(struct irq_data *d)
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{
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pci_msi_mask_irq(d);
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irq_chip_mask_parent(d);
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}
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static void mbi_unmask_msi_irq(struct irq_data *d)
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{
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pci_msi_unmask_irq(d);
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irq_chip_unmask_parent(d);
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}
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static struct irq_chip mbi_msi_irq_chip = {
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.name = "MSI",
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.irq_mask = mbi_mask_msi_irq,
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.irq_unmask = mbi_unmask_msi_irq,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_compose_msi_msg = mbi_compose_msi_msg,
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.irq_write_msi_msg = pci_msi_domain_write_msg,
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};
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static struct msi_domain_info mbi_msi_domain_info = {
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
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.chip = &mbi_msi_irq_chip,
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};
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static int mbi_allocate_pci_domain(struct irq_domain *nexus_domain,
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struct irq_domain **pci_domain)
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{
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*pci_domain = pci_msi_create_irq_domain(nexus_domain->parent->fwnode,
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&mbi_msi_domain_info,
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nexus_domain);
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if (!*pci_domain)
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return -ENOMEM;
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return 0;
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}
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#else
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static int mbi_allocate_pci_domain(struct irq_domain *nexus_domain,
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struct irq_domain **pci_domain)
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{
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*pci_domain = NULL;
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return 0;
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}
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#endif
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static void mbi_compose_mbi_msg(struct irq_data *data, struct msi_msg *msg)
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{
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mbi_compose_msi_msg(data, msg);
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msg[1].address_hi = upper_32_bits(mbi_phys_base + GICD_CLRSPI_NSR);
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msg[1].address_lo = lower_32_bits(mbi_phys_base + GICD_CLRSPI_NSR);
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msg[1].data = data->parent_data->hwirq;
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iommu_dma_map_msi_msg(data->irq, &msg[1]);
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}
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/* Platform-MSI specific irqchip */
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static struct irq_chip mbi_pmsi_irq_chip = {
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.name = "pMSI",
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.irq_set_type = irq_chip_set_type_parent,
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.irq_compose_msi_msg = mbi_compose_mbi_msg,
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.flags = IRQCHIP_SUPPORTS_LEVEL_MSI,
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};
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static struct msi_domain_ops mbi_pmsi_ops = {
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};
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static struct msi_domain_info mbi_pmsi_domain_info = {
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_LEVEL_CAPABLE),
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.ops = &mbi_pmsi_ops,
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.chip = &mbi_pmsi_irq_chip,
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};
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static int mbi_allocate_domains(struct irq_domain *parent)
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{
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struct irq_domain *nexus_domain, *pci_domain, *plat_domain;
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int err;
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nexus_domain = irq_domain_create_tree(parent->fwnode,
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&mbi_domain_ops, NULL);
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if (!nexus_domain)
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return -ENOMEM;
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irq_domain_update_bus_token(nexus_domain, DOMAIN_BUS_NEXUS);
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nexus_domain->parent = parent;
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err = mbi_allocate_pci_domain(nexus_domain, &pci_domain);
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plat_domain = platform_msi_create_irq_domain(parent->fwnode,
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&mbi_pmsi_domain_info,
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nexus_domain);
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if (err || !plat_domain) {
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if (plat_domain)
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irq_domain_remove(plat_domain);
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if (pci_domain)
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irq_domain_remove(pci_domain);
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irq_domain_remove(nexus_domain);
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return -ENOMEM;
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}
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return 0;
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}
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int __init mbi_init(struct fwnode_handle *fwnode, struct irq_domain *parent)
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{
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struct device_node *np;
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const __be32 *reg;
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int ret, n;
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np = to_of_node(fwnode);
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if (!of_property_read_bool(np, "msi-controller"))
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return 0;
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n = of_property_count_elems_of_size(np, "mbi-ranges", sizeof(u32));
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if (n <= 0 || n % 2)
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return -EINVAL;
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mbi_range_nr = n / 2;
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mbi_ranges = kcalloc(mbi_range_nr, sizeof(*mbi_ranges), GFP_KERNEL);
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if (!mbi_ranges)
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return -ENOMEM;
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for (n = 0; n < mbi_range_nr; n++) {
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ret = of_property_read_u32_index(np, "mbi-ranges", n * 2,
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&mbi_ranges[n].spi_start);
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if (ret)
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goto err_free_mbi;
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ret = of_property_read_u32_index(np, "mbi-ranges", n * 2 + 1,
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&mbi_ranges[n].nr_spis);
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if (ret)
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goto err_free_mbi;
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mbi_ranges[n].bm = kcalloc(BITS_TO_LONGS(mbi_ranges[n].nr_spis),
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sizeof(long), GFP_KERNEL);
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if (!mbi_ranges[n].bm) {
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ret = -ENOMEM;
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goto err_free_mbi;
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}
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pr_info("MBI range [%d:%d]\n", mbi_ranges[n].spi_start,
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mbi_ranges[n].spi_start + mbi_ranges[n].nr_spis - 1);
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}
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reg = of_get_property(np, "mbi-alias", NULL);
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if (reg) {
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mbi_phys_base = of_translate_address(np, reg);
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if (mbi_phys_base == OF_BAD_ADDR) {
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ret = -ENXIO;
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goto err_free_mbi;
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}
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} else {
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struct resource res;
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if (of_address_to_resource(np, 0, &res)) {
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ret = -ENXIO;
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goto err_free_mbi;
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}
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mbi_phys_base = res.start;
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}
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pr_info("Using MBI frame %pa\n", &mbi_phys_base);
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ret = mbi_allocate_domains(parent);
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if (ret)
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goto err_free_mbi;
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return 0;
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err_free_mbi:
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if (mbi_ranges) {
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for (n = 0; n < mbi_range_nr; n++)
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kfree(mbi_ranges[n].bm);
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kfree(mbi_ranges);
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}
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return ret;
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}
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