forked from Minki/linux
0d5ff56677
Convert libata core layer and LLDs to use iomap. * managed iomap is used. Pointer to pcim_iomap_table() is cached at host->iomap and used through out LLDs. This basically replaces host->mmio_base. * if possible, pcim_iomap_regions() is used Most iomap operation conversions are taken from Jeff Garzik <jgarzik@pobox.com>'s iomap branch. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
316 lines
7.5 KiB
C
316 lines
7.5 KiB
C
/*
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* pata_winbond.c - Winbond VLB ATA controllers
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* (C) 2006 Red Hat <alan@redhat.com>
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*
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* Support for the Winbond 83759A when operating in advanced mode.
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* Multichip mode is not currently supported.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#include <linux/platform_device.h>
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#define DRV_NAME "pata_winbond"
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#define DRV_VERSION "0.0.1"
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#define NR_HOST 4 /* Two winbond controllers, two channels each */
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struct winbond_data {
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unsigned long config;
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struct platform_device *platform_dev;
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};
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static struct ata_host *winbond_host[NR_HOST];
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static struct winbond_data winbond_data[NR_HOST];
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static int nr_winbond_host;
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#ifdef MODULE
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static int probe_winbond = 1;
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#else
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static int probe_winbond;
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#endif
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static spinlock_t winbond_lock = SPIN_LOCK_UNLOCKED;
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static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
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{
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unsigned long flags;
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spin_lock_irqsave(&winbond_lock, flags);
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outb(reg, port + 0x01);
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outb(val, port + 0x02);
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spin_unlock_irqrestore(&winbond_lock, flags);
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}
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static u8 winbond_readcfg(unsigned long port, u8 reg)
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{
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u8 val;
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unsigned long flags;
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spin_lock_irqsave(&winbond_lock, flags);
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outb(reg, port + 0x01);
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val = inb(port + 0x02);
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spin_unlock_irqrestore(&winbond_lock, flags);
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return val;
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}
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static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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struct ata_timing t;
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struct winbond_data *winbond = ap->host->private_data;
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int active, recovery;
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u8 reg;
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int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
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reg = winbond_readcfg(winbond->config, 0x81);
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/* Get the timing data in cycles */
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if (reg & 0x40) /* Fast VLB bus, assume 50MHz */
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ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
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else
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ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
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active = (FIT(t.active, 3, 17) - 1) & 0x0F;
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recovery = (FIT(t.recover, 1, 15) + 1) & 0x0F;
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timing = (active << 4) | recovery;
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winbond_writecfg(winbond->config, timing, reg);
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/* Load the setup timing */
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reg = 0x35;
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if (adev->class != ATA_DEV_ATA)
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reg |= 0x08; /* FIFO off */
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if (!ata_pio_need_iordy(adev))
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reg |= 0x02; /* IORDY off */
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reg |= (FIT(t.setup, 0, 3) << 6);
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winbond_writecfg(winbond->config, timing + 1, reg);
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}
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static void winbond_data_xfer(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data)
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{
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struct ata_port *ap = adev->ap;
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int slop = buflen & 3;
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if (ata_id_has_dword_io(adev->id)) {
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if (write_data)
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iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
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else
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ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
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if (unlikely(slop)) {
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u32 pad;
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if (write_data) {
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memcpy(&pad, buf + buflen - slop, slop);
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pad = le32_to_cpu(pad);
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iowrite32(pad, ap->ioaddr.data_addr);
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} else {
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pad = ioread32(ap->ioaddr.data_addr);
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pad = cpu_to_le16(pad);
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memcpy(buf + buflen - slop, &pad, slop);
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}
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}
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} else
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ata_data_xfer(adev, buf, buflen, write_data);
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}
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static struct scsi_host_template winbond_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.slave_destroy = ata_scsi_slave_destroy,
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.bios_param = ata_std_bios_param,
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};
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static struct ata_port_operations winbond_port_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = winbond_set_piomode,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = ata_bmdma_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = winbond_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.port_start = ata_port_start,
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};
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/**
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* winbond_init_one - attach a winbond interface
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* @type: Type to display
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* @io: I/O port start
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* @irq: interrupt line
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* @fast: True if on a > 33Mhz VLB
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*
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* Register a VLB bus IDE interface. Such interfaces are PIO and we
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* assume do not support IRQ sharing.
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*/
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static __init int winbond_init_one(unsigned long port)
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{
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struct ata_probe_ent ae;
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struct platform_device *pdev;
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int ret;
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u8 reg;
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int i;
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reg = winbond_readcfg(port, 0x81);
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reg |= 0x80; /* jumpered mode off */
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winbond_writecfg(port, 0x81, reg);
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reg = winbond_readcfg(port, 0x83);
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reg |= 0xF0; /* local control */
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winbond_writecfg(port, 0x83, reg);
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reg = winbond_readcfg(port, 0x85);
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reg |= 0xF0; /* programmable timing */
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winbond_writecfg(port, 0x85, reg);
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reg = winbond_readcfg(port, 0x81);
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if (!(reg & 0x03)) /* Disabled */
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return 0;
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for (i = 0; i < 2 ; i ++) {
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unsigned long cmd_port = 0x1F0 - (0x80 * i);
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void __iomem *cmd_addr, *ctl_addr;
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if (reg & (1 << i)) {
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/*
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* Fill in a probe structure first of all
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*/
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pdev = platform_device_register_simple(DRV_NAME, nr_winbond_host, NULL, 0);
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if (IS_ERR(pdev))
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return PTR_ERR(pdev);
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cmd_addr = devm_ioport_map(&pdev->dev, cmd_port, 8);
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ctl_addr = devm_ioport_map(&pdev->dev, cmd_port + 0x0206, 1);
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if (!cmd_addr || !ctl_addr) {
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platform_device_unregister(pdev);
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return -ENOMEM;
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}
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memset(&ae, 0, sizeof(struct ata_probe_ent));
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INIT_LIST_HEAD(&ae.node);
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ae.dev = &pdev->dev;
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ae.port_ops = &winbond_port_ops;
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ae.pio_mask = 0x1F;
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ae.sht = &winbond_sht;
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ae.n_ports = 1;
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ae.irq = 14 + i;
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ae.irq_flags = 0;
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ae.port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST;
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ae.port[0].cmd_addr = cmd_addr;
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ae.port[0].altstatus_addr = ctl_addr;
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ae.port[0].ctl_addr = ctl_addr;
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ata_std_ports(&ae.port[0]);
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/*
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* Hook in a private data structure per channel
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*/
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ae.private_data = &winbond_data[nr_winbond_host];
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winbond_data[nr_winbond_host].config = port;
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winbond_data[nr_winbond_host].platform_dev = pdev;
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ret = ata_device_add(&ae);
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if (ret == 0) {
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platform_device_unregister(pdev);
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return -ENODEV;
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}
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winbond_host[nr_winbond_host++] = dev_get_drvdata(&pdev->dev);
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}
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}
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return 0;
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}
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/**
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* winbond_init - attach winbond interfaces
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*
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* Attach winbond IDE interfaces by scanning the ports it may occupy.
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*/
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static __init int winbond_init(void)
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{
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static const unsigned long config[2] = { 0x130, 0x1B0 };
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int ct = 0;
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int i;
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if (probe_winbond == 0)
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return -ENODEV;
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/*
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* Check both base addresses
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*/
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for (i = 0; i < 2; i++) {
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if (probe_winbond & (1<<i)) {
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int ret = 0;
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unsigned long port = config[i];
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if (request_region(port, 2, "pata_winbond")) {
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ret = winbond_init_one(port);
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if(ret <= 0)
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release_region(port, 2);
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else ct+= ret;
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}
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}
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}
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if (ct != 0)
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return 0;
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return -ENODEV;
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}
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static __exit void winbond_exit(void)
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{
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int i;
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for (i = 0; i < nr_winbond_host; i++) {
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ata_host_detach(winbond_host[i]);
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release_region(winbond_data[i].config, 2);
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platform_device_unregister(winbond_data[i].platform_dev);
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}
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}
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("low-level driver for Winbond VL ATA");
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MODULE_LICENSE("GPL");
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MODULE_VERSION(DRV_VERSION);
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module_init(winbond_init);
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module_exit(winbond_exit);
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module_param(probe_winbond, int, 0);
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