forked from Minki/linux
7ad295d519
When using following operations: date -s "21190910 19:20:00" hwclock -w to change date from 2019 to 2119 for test, it will fail on Hygon Dhyana and AMD Zen CPUs, while the same operations run ok on Intel i7 platform. MC146818 driver use function mc146818_set_time() to set register RTC_FREQ_SELECT(RTC_REG_A)'s bit4-bit6 field which means divider stage reset value on Intel platform to 0x7. While AMD/Hygon RTC_REG_A(0Ah)'s bit4 is defined as DV0 [Reference]: DV0 = 0 selects Bank 0, DV0 = 1 selects Bank 1. Bit5-bit6 is defined as reserved. DV0 is set to 1, it will select Bank 1, which will disable AltCentury register(0x32) access. As UEFI pass acpi_gbl_FADT.century 0x32 (AltCentury), the CMOS write will be failed on code: CMOS_WRITE(century, acpi_gbl_FADT.century). Correct RTC_REG_A bank select bit(DV0) to 0 on AMD/Hygon CPUs, it will enable AltCentury(0x32) register writing and finally setup century as expected. Test results on Intel i7, AMD EPYC(17h) and Hygon machine show that it works as expected. Compiling for sparc64 and alpha architectures are passed. Reference: https://www.amd.com/system/files/TechDocs/51192_Bolton_FCH_RRG.pdf section: 3.13 Real Time Clock (RTC) Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Jinke Fan <fanjinke@hygon.cn> Link: https://lore.kernel.org/r/20191105083943.115320-1-fanjinke@hygon.cn Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
213 lines
5.4 KiB
C
213 lines
5.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/bcd.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/mc146818rtc.h>
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#ifdef CONFIG_ACPI
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#include <linux/acpi.h>
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#endif
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/*
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* Returns true if a clock update is in progress
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*/
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static inline unsigned char mc146818_is_updating(void)
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{
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unsigned char uip;
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unsigned long flags;
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spin_lock_irqsave(&rtc_lock, flags);
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uip = (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP);
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spin_unlock_irqrestore(&rtc_lock, flags);
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return uip;
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}
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unsigned int mc146818_get_time(struct rtc_time *time)
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{
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unsigned char ctrl;
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unsigned long flags;
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unsigned char century = 0;
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#ifdef CONFIG_MACH_DECSTATION
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unsigned int real_year;
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#endif
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/*
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* read RTC once any update in progress is done. The update
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* can take just over 2ms. We wait 20ms. There is no need to
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* to poll-wait (up to 1s - eeccch) for the falling edge of RTC_UIP.
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* If you need to know *exactly* when a second has started, enable
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* periodic update complete interrupts, (via ioctl) and then
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* immediately read /dev/rtc which will block until you get the IRQ.
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* Once the read clears, read the RTC time (again via ioctl). Easy.
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*/
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if (mc146818_is_updating())
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mdelay(20);
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/*
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* Only the values that we read from the RTC are set. We leave
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* tm_wday, tm_yday and tm_isdst untouched. Even though the
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* RTC has RTC_DAY_OF_WEEK, we ignore it, as it is only updated
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* by the RTC when initially set to a non-zero value.
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*/
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spin_lock_irqsave(&rtc_lock, flags);
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time->tm_sec = CMOS_READ(RTC_SECONDS);
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time->tm_min = CMOS_READ(RTC_MINUTES);
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time->tm_hour = CMOS_READ(RTC_HOURS);
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time->tm_mday = CMOS_READ(RTC_DAY_OF_MONTH);
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time->tm_mon = CMOS_READ(RTC_MONTH);
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time->tm_year = CMOS_READ(RTC_YEAR);
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#ifdef CONFIG_MACH_DECSTATION
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real_year = CMOS_READ(RTC_DEC_YEAR);
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#endif
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#ifdef CONFIG_ACPI
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if (acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID &&
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acpi_gbl_FADT.century)
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century = CMOS_READ(acpi_gbl_FADT.century);
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#endif
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ctrl = CMOS_READ(RTC_CONTROL);
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spin_unlock_irqrestore(&rtc_lock, flags);
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if (!(ctrl & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
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{
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time->tm_sec = bcd2bin(time->tm_sec);
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time->tm_min = bcd2bin(time->tm_min);
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time->tm_hour = bcd2bin(time->tm_hour);
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time->tm_mday = bcd2bin(time->tm_mday);
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time->tm_mon = bcd2bin(time->tm_mon);
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time->tm_year = bcd2bin(time->tm_year);
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century = bcd2bin(century);
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}
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#ifdef CONFIG_MACH_DECSTATION
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time->tm_year += real_year - 72;
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#endif
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if (century > 20)
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time->tm_year += (century - 19) * 100;
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/*
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* Account for differences between how the RTC uses the values
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* and how they are defined in a struct rtc_time;
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*/
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if (time->tm_year <= 69)
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time->tm_year += 100;
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time->tm_mon--;
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return RTC_24H;
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}
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EXPORT_SYMBOL_GPL(mc146818_get_time);
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/* Set the current date and time in the real time clock. */
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int mc146818_set_time(struct rtc_time *time)
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{
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unsigned long flags;
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unsigned char mon, day, hrs, min, sec;
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unsigned char save_control, save_freq_select;
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unsigned int yrs;
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#ifdef CONFIG_MACH_DECSTATION
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unsigned int real_yrs, leap_yr;
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#endif
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unsigned char century = 0;
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yrs = time->tm_year;
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mon = time->tm_mon + 1; /* tm_mon starts at zero */
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day = time->tm_mday;
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hrs = time->tm_hour;
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min = time->tm_min;
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sec = time->tm_sec;
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if (yrs > 255) /* They are unsigned */
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return -EINVAL;
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spin_lock_irqsave(&rtc_lock, flags);
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#ifdef CONFIG_MACH_DECSTATION
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real_yrs = yrs;
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leap_yr = ((!((yrs + 1900) % 4) && ((yrs + 1900) % 100)) ||
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!((yrs + 1900) % 400));
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yrs = 72;
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/*
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* We want to keep the year set to 73 until March
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* for non-leap years, so that Feb, 29th is handled
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* correctly.
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*/
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if (!leap_yr && mon < 3) {
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real_yrs--;
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yrs = 73;
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}
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#endif
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#ifdef CONFIG_ACPI
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if (acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID &&
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acpi_gbl_FADT.century) {
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century = (yrs + 1900) / 100;
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yrs %= 100;
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}
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#endif
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/* These limits and adjustments are independent of
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* whether the chip is in binary mode or not.
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*/
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if (yrs > 169) {
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spin_unlock_irqrestore(&rtc_lock, flags);
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return -EINVAL;
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}
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if (yrs >= 100)
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yrs -= 100;
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if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY)
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|| RTC_ALWAYS_BCD) {
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sec = bin2bcd(sec);
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min = bin2bcd(min);
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hrs = bin2bcd(hrs);
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day = bin2bcd(day);
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mon = bin2bcd(mon);
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yrs = bin2bcd(yrs);
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century = bin2bcd(century);
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}
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save_control = CMOS_READ(RTC_CONTROL);
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CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
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save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
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#ifdef CONFIG_X86
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if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
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boot_cpu_data.x86 == 0x17) ||
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boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
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CMOS_WRITE((save_freq_select & (~RTC_DIV_RESET2)),
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RTC_FREQ_SELECT);
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save_freq_select &= ~RTC_DIV_RESET2;
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} else
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CMOS_WRITE((save_freq_select | RTC_DIV_RESET2),
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RTC_FREQ_SELECT);
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#else
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CMOS_WRITE((save_freq_select | RTC_DIV_RESET2), RTC_FREQ_SELECT);
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#endif
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#ifdef CONFIG_MACH_DECSTATION
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CMOS_WRITE(real_yrs, RTC_DEC_YEAR);
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#endif
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CMOS_WRITE(yrs, RTC_YEAR);
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CMOS_WRITE(mon, RTC_MONTH);
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CMOS_WRITE(day, RTC_DAY_OF_MONTH);
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CMOS_WRITE(hrs, RTC_HOURS);
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CMOS_WRITE(min, RTC_MINUTES);
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CMOS_WRITE(sec, RTC_SECONDS);
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#ifdef CONFIG_ACPI
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if (acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID &&
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acpi_gbl_FADT.century)
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CMOS_WRITE(century, acpi_gbl_FADT.century);
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#endif
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CMOS_WRITE(save_control, RTC_CONTROL);
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CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
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spin_unlock_irqrestore(&rtc_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(mc146818_set_time);
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