forked from Minki/linux
f8b410e369
This renames the "gpio-aspeed" driver to conform with other
GPIO drivers as "gpio-aspeed-sgpio.c". All GPIO drivers
should start with the string "gpio-" no special exceptions.
Also the Kconfig and Makefile entries should normally
go with the driver but I missed this in my review, sorry
for mistake. "CONFIG_GPIO_ASPEED_SGPIO" is used to
activate this driver.
Cc: Hongwei Zhang <hongweiz@ami.com>
Fixes: 7db47faae7
("gpio: aspeed: Add SGPIO driver")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190927114833.12551-1-linus.walleij@linaro.org
534 lines
13 KiB
C
534 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2019 American Megatrends International LLC.
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*
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* Author: Karthikeyan Mani <karthikeyanm@amiindia.co.in>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/gpio/driver.h>
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#include <linux/hashtable.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#define MAX_NR_SGPIO 80
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#define ASPEED_SGPIO_CTRL 0x54
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#define ASPEED_SGPIO_PINS_MASK GENMASK(9, 6)
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#define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16)
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#define ASPEED_SGPIO_ENABLE BIT(0)
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struct aspeed_sgpio {
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struct gpio_chip chip;
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struct clk *pclk;
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spinlock_t lock;
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void __iomem *base;
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uint32_t dir_in[3];
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int irq;
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};
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struct aspeed_sgpio_bank {
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uint16_t val_regs;
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uint16_t rdata_reg;
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uint16_t irq_regs;
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const char names[4][3];
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};
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/*
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* Note: The "value" register returns the input value when the GPIO is
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* configured as an input.
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*
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* The "rdata" register returns the output value when the GPIO is
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* configured as an output.
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*/
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static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
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{
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.val_regs = 0x0000,
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.rdata_reg = 0x0070,
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.irq_regs = 0x0004,
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.names = { "A", "B", "C", "D" },
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},
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{
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.val_regs = 0x001C,
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.rdata_reg = 0x0074,
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.irq_regs = 0x0020,
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.names = { "E", "F", "G", "H" },
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},
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{
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.val_regs = 0x0038,
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.rdata_reg = 0x0078,
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.irq_regs = 0x003C,
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.names = { "I", "J" },
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},
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};
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enum aspeed_sgpio_reg {
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reg_val,
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reg_rdata,
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reg_irq_enable,
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reg_irq_type0,
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reg_irq_type1,
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reg_irq_type2,
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reg_irq_status,
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};
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#define GPIO_VAL_VALUE 0x00
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#define GPIO_IRQ_ENABLE 0x00
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#define GPIO_IRQ_TYPE0 0x04
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#define GPIO_IRQ_TYPE1 0x08
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#define GPIO_IRQ_TYPE2 0x0C
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#define GPIO_IRQ_STATUS 0x10
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static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
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const struct aspeed_sgpio_bank *bank,
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const enum aspeed_sgpio_reg reg)
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{
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switch (reg) {
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case reg_val:
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return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
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case reg_rdata:
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return gpio->base + bank->rdata_reg;
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case reg_irq_enable:
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return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
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case reg_irq_type0:
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return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
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case reg_irq_type1:
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return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
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case reg_irq_type2:
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return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
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case reg_irq_status:
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return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
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default:
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/* acturally if code runs to here, it's an error case */
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BUG_ON(1);
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}
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}
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#define GPIO_BANK(x) ((x) >> 5)
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#define GPIO_OFFSET(x) ((x) & 0x1f)
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#define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
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static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
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{
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unsigned int bank = GPIO_BANK(offset);
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WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
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return &aspeed_sgpio_banks[bank];
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}
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static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
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{
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struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
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const struct aspeed_sgpio_bank *bank = to_bank(offset);
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unsigned long flags;
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enum aspeed_sgpio_reg reg;
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bool is_input;
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int rc = 0;
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spin_lock_irqsave(&gpio->lock, flags);
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is_input = gpio->dir_in[GPIO_BANK(offset)] & GPIO_BIT(offset);
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reg = is_input ? reg_val : reg_rdata;
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rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
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spin_unlock_irqrestore(&gpio->lock, flags);
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return rc;
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}
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static void sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
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{
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struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
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const struct aspeed_sgpio_bank *bank = to_bank(offset);
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void __iomem *addr;
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u32 reg = 0;
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addr = bank_reg(gpio, bank, reg_val);
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reg = ioread32(addr);
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if (val)
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reg |= GPIO_BIT(offset);
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else
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reg &= ~GPIO_BIT(offset);
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iowrite32(reg, addr);
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}
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static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
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{
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struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&gpio->lock, flags);
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sgpio_set_value(gc, offset, val);
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spin_unlock_irqrestore(&gpio->lock, flags);
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}
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static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
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{
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struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&gpio->lock, flags);
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gpio->dir_in[GPIO_BANK(offset)] |= GPIO_BIT(offset);
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spin_unlock_irqrestore(&gpio->lock, flags);
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return 0;
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}
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static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
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{
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struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&gpio->lock, flags);
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gpio->dir_in[GPIO_BANK(offset)] &= ~GPIO_BIT(offset);
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sgpio_set_value(gc, offset, val);
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spin_unlock_irqrestore(&gpio->lock, flags);
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return 0;
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}
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static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
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{
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int dir_status;
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struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&gpio->lock, flags);
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dir_status = gpio->dir_in[GPIO_BANK(offset)] & GPIO_BIT(offset);
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spin_unlock_irqrestore(&gpio->lock, flags);
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return dir_status;
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}
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static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
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struct aspeed_sgpio **gpio,
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const struct aspeed_sgpio_bank **bank,
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u32 *bit, int *offset)
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{
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struct aspeed_sgpio *internal;
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*offset = irqd_to_hwirq(d);
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internal = irq_data_get_irq_chip_data(d);
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WARN_ON(!internal);
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*gpio = internal;
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*bank = to_bank(*offset);
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*bit = GPIO_BIT(*offset);
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}
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static void aspeed_sgpio_irq_ack(struct irq_data *d)
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{
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const struct aspeed_sgpio_bank *bank;
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struct aspeed_sgpio *gpio;
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unsigned long flags;
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void __iomem *status_addr;
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int offset;
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u32 bit;
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irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
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status_addr = bank_reg(gpio, bank, reg_irq_status);
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spin_lock_irqsave(&gpio->lock, flags);
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iowrite32(bit, status_addr);
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spin_unlock_irqrestore(&gpio->lock, flags);
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}
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static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set)
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{
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const struct aspeed_sgpio_bank *bank;
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struct aspeed_sgpio *gpio;
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unsigned long flags;
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u32 reg, bit;
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void __iomem *addr;
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int offset;
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irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
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addr = bank_reg(gpio, bank, reg_irq_enable);
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spin_lock_irqsave(&gpio->lock, flags);
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reg = ioread32(addr);
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if (set)
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reg |= bit;
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else
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reg &= ~bit;
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iowrite32(reg, addr);
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spin_unlock_irqrestore(&gpio->lock, flags);
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}
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static void aspeed_sgpio_irq_mask(struct irq_data *d)
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{
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aspeed_sgpio_irq_set_mask(d, false);
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}
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static void aspeed_sgpio_irq_unmask(struct irq_data *d)
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{
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aspeed_sgpio_irq_set_mask(d, true);
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}
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static int aspeed_sgpio_set_type(struct irq_data *d, unsigned int type)
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{
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u32 type0 = 0;
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u32 type1 = 0;
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u32 type2 = 0;
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u32 bit, reg;
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const struct aspeed_sgpio_bank *bank;
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irq_flow_handler_t handler;
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struct aspeed_sgpio *gpio;
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unsigned long flags;
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void __iomem *addr;
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int offset;
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irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_BOTH:
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type2 |= bit;
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/* fall through */
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case IRQ_TYPE_EDGE_RISING:
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type0 |= bit;
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/* fall through */
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case IRQ_TYPE_EDGE_FALLING:
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handler = handle_edge_irq;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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type0 |= bit;
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/* fall through */
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case IRQ_TYPE_LEVEL_LOW:
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type1 |= bit;
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handler = handle_level_irq;
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break;
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default:
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return -EINVAL;
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}
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spin_lock_irqsave(&gpio->lock, flags);
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addr = bank_reg(gpio, bank, reg_irq_type0);
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reg = ioread32(addr);
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reg = (reg & ~bit) | type0;
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iowrite32(reg, addr);
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addr = bank_reg(gpio, bank, reg_irq_type1);
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reg = ioread32(addr);
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reg = (reg & ~bit) | type1;
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iowrite32(reg, addr);
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addr = bank_reg(gpio, bank, reg_irq_type2);
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reg = ioread32(addr);
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reg = (reg & ~bit) | type2;
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iowrite32(reg, addr);
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spin_unlock_irqrestore(&gpio->lock, flags);
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irq_set_handler_locked(d, handler);
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return 0;
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}
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static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct irq_chip *ic = irq_desc_get_chip(desc);
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struct aspeed_sgpio *data = gpiochip_get_data(gc);
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unsigned int i, p, girq;
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unsigned long reg;
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chained_irq_enter(ic, desc);
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for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
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const struct aspeed_sgpio_bank *bank = &aspeed_sgpio_banks[i];
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reg = ioread32(bank_reg(data, bank, reg_irq_status));
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for_each_set_bit(p, ®, 32) {
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girq = irq_find_mapping(gc->irq.domain, i * 32 + p);
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generic_handle_irq(girq);
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}
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}
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chained_irq_exit(ic, desc);
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}
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static struct irq_chip aspeed_sgpio_irqchip = {
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.name = "aspeed-sgpio",
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.irq_ack = aspeed_sgpio_irq_ack,
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.irq_mask = aspeed_sgpio_irq_mask,
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.irq_unmask = aspeed_sgpio_irq_unmask,
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.irq_set_type = aspeed_sgpio_set_type,
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};
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static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
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struct platform_device *pdev)
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{
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int rc, i;
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const struct aspeed_sgpio_bank *bank;
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struct gpio_irq_chip *irq;
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rc = platform_get_irq(pdev, 0);
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if (rc < 0)
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return rc;
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gpio->irq = rc;
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/* Disable IRQ and clear Interrupt status registers for all SPGIO Pins. */
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for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
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bank = &aspeed_sgpio_banks[i];
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/* disable irq enable bits */
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iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable));
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/* clear status bits */
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iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status));
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}
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irq = &gpio->chip.irq;
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irq->chip = &aspeed_sgpio_irqchip;
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irq->handler = handle_bad_irq;
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irq->default_type = IRQ_TYPE_NONE;
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irq->parent_handler = aspeed_sgpio_irq_handler;
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irq->parent_handler_data = gpio;
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irq->parents = &gpio->irq;
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irq->num_parents = 1;
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/* set IRQ settings and Enable Interrupt */
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for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
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bank = &aspeed_sgpio_banks[i];
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/* set falling or level-low irq */
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iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0));
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/* trigger type is edge */
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iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1));
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/* dual edge trigger mode. */
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iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_type2));
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/* enable irq */
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iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_enable));
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}
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return 0;
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}
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static const struct of_device_id aspeed_sgpio_of_table[] = {
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{ .compatible = "aspeed,ast2400-sgpio" },
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{ .compatible = "aspeed,ast2500-sgpio" },
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{}
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};
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MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
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static int __init aspeed_sgpio_probe(struct platform_device *pdev)
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{
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struct aspeed_sgpio *gpio;
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u32 nr_gpios, sgpio_freq, sgpio_clk_div;
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int rc;
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unsigned long apb_freq;
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gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
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if (!gpio)
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return -ENOMEM;
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gpio->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(gpio->base))
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return PTR_ERR(gpio->base);
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rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios);
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if (rc < 0) {
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dev_err(&pdev->dev, "Could not read ngpios property\n");
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return -EINVAL;
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} else if (nr_gpios > MAX_NR_SGPIO) {
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dev_err(&pdev->dev, "Number of GPIOs exceeds the maximum of %d: %d\n",
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MAX_NR_SGPIO, nr_gpios);
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return -EINVAL;
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}
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rc = of_property_read_u32(pdev->dev.of_node, "bus-frequency", &sgpio_freq);
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if (rc < 0) {
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dev_err(&pdev->dev, "Could not read bus-frequency property\n");
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return -EINVAL;
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}
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gpio->pclk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(gpio->pclk)) {
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dev_err(&pdev->dev, "devm_clk_get failed\n");
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return PTR_ERR(gpio->pclk);
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}
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apb_freq = clk_get_rate(gpio->pclk);
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/*
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* From the datasheet,
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* SGPIO period = 1/PCLK * 2 * (GPIO254[31:16] + 1)
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* period = 2 * (GPIO254[31:16] + 1) / PCLK
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* frequency = 1 / (2 * (GPIO254[31:16] + 1) / PCLK)
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* frequency = PCLK / (2 * (GPIO254[31:16] + 1))
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* frequency * 2 * (GPIO254[31:16] + 1) = PCLK
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* GPIO254[31:16] = PCLK / (frequency * 2) - 1
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*/
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if (sgpio_freq == 0)
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return -EINVAL;
|
|
|
|
sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1;
|
|
|
|
if (sgpio_clk_div > (1 << 16) - 1)
|
|
return -EINVAL;
|
|
|
|
iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) |
|
|
FIELD_PREP(ASPEED_SGPIO_PINS_MASK, (nr_gpios / 8)) |
|
|
ASPEED_SGPIO_ENABLE,
|
|
gpio->base + ASPEED_SGPIO_CTRL);
|
|
|
|
spin_lock_init(&gpio->lock);
|
|
|
|
gpio->chip.parent = &pdev->dev;
|
|
gpio->chip.ngpio = nr_gpios;
|
|
gpio->chip.direction_input = aspeed_sgpio_dir_in;
|
|
gpio->chip.direction_output = aspeed_sgpio_dir_out;
|
|
gpio->chip.get_direction = aspeed_sgpio_get_direction;
|
|
gpio->chip.request = NULL;
|
|
gpio->chip.free = NULL;
|
|
gpio->chip.get = aspeed_sgpio_get;
|
|
gpio->chip.set = aspeed_sgpio_set;
|
|
gpio->chip.set_config = NULL;
|
|
gpio->chip.label = dev_name(&pdev->dev);
|
|
gpio->chip.base = -1;
|
|
|
|
/* set all SGPIO pins as input (1). */
|
|
memset(gpio->dir_in, 0xff, sizeof(gpio->dir_in));
|
|
|
|
aspeed_sgpio_setup_irqs(gpio, pdev);
|
|
|
|
rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver aspeed_sgpio_driver = {
|
|
.driver = {
|
|
.name = KBUILD_MODNAME,
|
|
.of_match_table = aspeed_sgpio_of_table,
|
|
},
|
|
};
|
|
|
|
module_platform_driver_probe(aspeed_sgpio_driver, aspeed_sgpio_probe);
|
|
MODULE_DESCRIPTION("Aspeed Serial GPIO Driver");
|
|
MODULE_LICENSE("GPL");
|