Thierry Reding 0d0d498265 drm/nouveau/ltc/gp10b: Add custom L2 cache implementation ... There are extra registers that need to be programmed to make the level 2 cache work on GP10B, such as the stream ID register that is used when an SMMU is used to translate memory addresses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>		2020-01-15 10:49:59 +10:00
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nvif	drm/nouveau: fix bogus GPL-2 license header	2019-07-19 16:26:50 +10:00
nvkm	drm/nouveau/ltc/gp10b: Add custom L2 cache implementation	2020-01-15 10:49:59 +10:00