forked from Minki/linux
6fdc99a224
Seems nobody else is checking/testing this case as it keeps getting horked. If we have no BAR4 mapping on an SFF controller this is *NOT* an error, it just means it isn't doing BMDMA. Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
916 lines
23 KiB
C
916 lines
23 KiB
C
/*
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* libata-sff.c - helper library for PCI IDE BMDMA
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*
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* Maintained by: Jeff Garzik <jgarzik@pobox.com>
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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* Copyright 2003-2006 Red Hat, Inc. All rights reserved.
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* Copyright 2003-2006 Jeff Garzik
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/DocBook/libata.*
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*
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* Hardware documentation available from http://www.t13.org/ and
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* http://www.sata-io.org/
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*
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/libata.h>
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#include "libata.h"
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/**
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* ata_irq_on - Enable interrupts on a port.
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* @ap: Port on which interrupts are enabled.
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*
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* Enable interrupts on a legacy IDE device using MMIO or PIO,
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* wait for idle, clear any pending interrupts.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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u8 ata_irq_on(struct ata_port *ap)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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u8 tmp;
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ap->ctl &= ~ATA_NIEN;
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ap->last_ctl = ap->ctl;
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iowrite8(ap->ctl, ioaddr->ctl_addr);
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tmp = ata_wait_idle(ap);
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ap->ops->irq_clear(ap);
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return tmp;
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}
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u8 ata_dummy_irq_on (struct ata_port *ap) { return 0; }
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/**
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* ata_irq_ack - Acknowledge a device interrupt.
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* @ap: Port on which interrupts are enabled.
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*
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* Wait up to 10 ms for legacy IDE device to become idle (BUSY
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* or BUSY+DRQ clear). Obtain dma status and port status from
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* device. Clear the interrupt. Return port status.
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*
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* LOCKING:
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*/
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u8 ata_irq_ack(struct ata_port *ap, unsigned int chk_drq)
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{
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unsigned int bits = chk_drq ? ATA_BUSY | ATA_DRQ : ATA_BUSY;
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u8 host_stat = 0, post_stat = 0, status;
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status = ata_busy_wait(ap, bits, 1000);
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if (status & bits)
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if (ata_msg_err(ap))
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printk(KERN_ERR "abnormal status 0x%X\n", status);
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if (ap->ioaddr.bmdma_addr) {
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/* get controller status; clear intr, err bits */
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host_stat = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
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iowrite8(host_stat | ATA_DMA_INTR | ATA_DMA_ERR,
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ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
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post_stat = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
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}
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if (ata_msg_intr(ap))
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printk(KERN_INFO "%s: irq ack: host_stat 0x%X, new host_stat 0x%X, drv_stat 0x%X\n",
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__FUNCTION__,
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host_stat, post_stat, status);
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return status;
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}
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u8 ata_dummy_irq_ack(struct ata_port *ap, unsigned int chk_drq) { return 0; }
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/**
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* ata_tf_load - send taskfile registers to host controller
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* @ap: Port to which output is sent
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* @tf: ATA taskfile register set
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*
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* Outputs ATA taskfile to standard ATA host controller.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
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if (tf->ctl != ap->last_ctl) {
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iowrite8(tf->ctl, ioaddr->ctl_addr);
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ap->last_ctl = tf->ctl;
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ata_wait_idle(ap);
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}
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if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
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iowrite8(tf->hob_feature, ioaddr->feature_addr);
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iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
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iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
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iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
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iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
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VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
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tf->hob_feature,
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tf->hob_nsect,
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tf->hob_lbal,
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tf->hob_lbam,
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tf->hob_lbah);
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}
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if (is_addr) {
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iowrite8(tf->feature, ioaddr->feature_addr);
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iowrite8(tf->nsect, ioaddr->nsect_addr);
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iowrite8(tf->lbal, ioaddr->lbal_addr);
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iowrite8(tf->lbam, ioaddr->lbam_addr);
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iowrite8(tf->lbah, ioaddr->lbah_addr);
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VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
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tf->feature,
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tf->nsect,
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tf->lbal,
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tf->lbam,
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tf->lbah);
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}
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if (tf->flags & ATA_TFLAG_DEVICE) {
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iowrite8(tf->device, ioaddr->device_addr);
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VPRINTK("device 0x%X\n", tf->device);
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}
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ata_wait_idle(ap);
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}
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/**
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* ata_exec_command - issue ATA command to host controller
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* @ap: port to which command is being issued
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* @tf: ATA taskfile register set
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*
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* Issues ATA command, with proper synchronization with interrupt
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* handler / other threads.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
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{
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DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
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iowrite8(tf->command, ap->ioaddr.command_addr);
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ata_pause(ap);
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}
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/**
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* ata_tf_read - input device's ATA taskfile shadow registers
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* @ap: Port from which input is read
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* @tf: ATA taskfile register set for storing input
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*
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* Reads ATA taskfile registers for currently-selected device
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* into @tf.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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tf->command = ata_check_status(ap);
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tf->feature = ioread8(ioaddr->error_addr);
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tf->nsect = ioread8(ioaddr->nsect_addr);
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tf->lbal = ioread8(ioaddr->lbal_addr);
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tf->lbam = ioread8(ioaddr->lbam_addr);
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tf->lbah = ioread8(ioaddr->lbah_addr);
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tf->device = ioread8(ioaddr->device_addr);
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if (tf->flags & ATA_TFLAG_LBA48) {
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iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
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tf->hob_feature = ioread8(ioaddr->error_addr);
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tf->hob_nsect = ioread8(ioaddr->nsect_addr);
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tf->hob_lbal = ioread8(ioaddr->lbal_addr);
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tf->hob_lbam = ioread8(ioaddr->lbam_addr);
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tf->hob_lbah = ioread8(ioaddr->lbah_addr);
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iowrite8(tf->ctl, ioaddr->ctl_addr);
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ap->last_ctl = tf->ctl;
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}
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}
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/**
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* ata_check_status - Read device status reg & clear interrupt
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* @ap: port where the device is
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*
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* Reads ATA taskfile status register for currently-selected device
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* and return its value. This also clears pending interrupts
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* from this device
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*
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* LOCKING:
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* Inherited from caller.
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*/
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u8 ata_check_status(struct ata_port *ap)
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{
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return ioread8(ap->ioaddr.status_addr);
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}
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/**
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* ata_altstatus - Read device alternate status reg
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* @ap: port where the device is
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*
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* Reads ATA taskfile alternate status register for
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* currently-selected device and return its value.
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*
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* Note: may NOT be used as the check_altstatus() entry in
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* ata_port_operations.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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u8 ata_altstatus(struct ata_port *ap)
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{
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if (ap->ops->check_altstatus)
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return ap->ops->check_altstatus(ap);
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return ioread8(ap->ioaddr.altstatus_addr);
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}
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/**
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* ata_bmdma_setup - Set up PCI IDE BMDMA transaction
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* @qc: Info associated with this ATA transaction.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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void ata_bmdma_setup(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
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u8 dmactl;
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/* load PRD table addr. */
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mb(); /* make sure PRD table writes are visible to controller */
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iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
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/* specify data direction, triple-check start bit is clear */
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dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
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if (!rw)
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dmactl |= ATA_DMA_WR;
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iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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/* issue r/w command */
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ap->ops->exec_command(ap, &qc->tf);
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}
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/**
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* ata_bmdma_start - Start a PCI IDE BMDMA transaction
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* @qc: Info associated with this ATA transaction.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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void ata_bmdma_start (struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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u8 dmactl;
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/* start host DMA transaction */
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dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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/* Strictly, one may wish to issue a readb() here, to
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* flush the mmio write. However, control also passes
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* to the hardware at this point, and it will interrupt
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* us when we are to resume control. So, in effect,
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* we don't care when the mmio write flushes.
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* Further, a read of the DMA status register _immediately_
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* following the write may not be what certain flaky hardware
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* is expected, so I think it is best to not add a readb()
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* without first all the MMIO ATA cards/mobos.
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* Or maybe I'm just being paranoid.
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*/
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}
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/**
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* ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
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* @ap: Port associated with this ATA transaction.
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*
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* Clear interrupt and error flags in DMA status register.
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*
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* May be used as the irq_clear() entry in ata_port_operations.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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void ata_bmdma_irq_clear(struct ata_port *ap)
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{
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void __iomem *mmio = ap->ioaddr.bmdma_addr;
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if (!mmio)
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return;
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iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
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}
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/**
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* ata_bmdma_status - Read PCI IDE BMDMA status
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* @ap: Port associated with this ATA transaction.
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*
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* Read and return BMDMA status register.
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*
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* May be used as the bmdma_status() entry in ata_port_operations.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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u8 ata_bmdma_status(struct ata_port *ap)
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{
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return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
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}
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/**
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* ata_bmdma_stop - Stop PCI IDE BMDMA transfer
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* @qc: Command we are ending DMA for
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*
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* Clears the ATA_DMA_START flag in the dma control register
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*
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* May be used as the bmdma_stop() entry in ata_port_operations.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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void ata_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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void __iomem *mmio = ap->ioaddr.bmdma_addr;
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/* clear start/stop bit */
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iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
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mmio + ATA_DMA_CMD);
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/* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
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ata_altstatus(ap); /* dummy read */
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}
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/**
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* ata_bmdma_freeze - Freeze BMDMA controller port
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* @ap: port to freeze
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*
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* Freeze BMDMA controller port.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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void ata_bmdma_freeze(struct ata_port *ap)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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ap->ctl |= ATA_NIEN;
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ap->last_ctl = ap->ctl;
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iowrite8(ap->ctl, ioaddr->ctl_addr);
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/* Under certain circumstances, some controllers raise IRQ on
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* ATA_NIEN manipulation. Also, many controllers fail to mask
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* previously pending IRQ on ATA_NIEN assertion. Clear it.
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*/
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ata_chk_status(ap);
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ap->ops->irq_clear(ap);
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}
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/**
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* ata_bmdma_thaw - Thaw BMDMA controller port
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* @ap: port to thaw
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*
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* Thaw BMDMA controller port.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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void ata_bmdma_thaw(struct ata_port *ap)
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{
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/* clear & re-enable interrupts */
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ata_chk_status(ap);
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ap->ops->irq_clear(ap);
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ap->ops->irq_on(ap);
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}
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/**
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* ata_bmdma_drive_eh - Perform EH with given methods for BMDMA controller
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* @ap: port to handle error for
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* @prereset: prereset method (can be NULL)
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* @softreset: softreset method (can be NULL)
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* @hardreset: hardreset method (can be NULL)
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* @postreset: postreset method (can be NULL)
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*
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* Handle error for ATA BMDMA controller. It can handle both
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* PATA and SATA controllers. Many controllers should be able to
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* use this EH as-is or with some added handling before and
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* after.
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*
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* This function is intended to be used for constructing
|
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* ->error_handler callback by low level drivers.
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*
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* LOCKING:
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* Kernel thread context (may sleep)
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*/
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void ata_bmdma_drive_eh(struct ata_port *ap, ata_prereset_fn_t prereset,
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ata_reset_fn_t softreset, ata_reset_fn_t hardreset,
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ata_postreset_fn_t postreset)
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{
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struct ata_queued_cmd *qc;
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unsigned long flags;
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int thaw = 0;
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qc = __ata_qc_from_tag(ap, ap->active_tag);
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if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
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qc = NULL;
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/* reset PIO HSM and stop DMA engine */
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spin_lock_irqsave(ap->lock, flags);
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ap->hsm_task_state = HSM_ST_IDLE;
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if (qc && (qc->tf.protocol == ATA_PROT_DMA ||
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qc->tf.protocol == ATA_PROT_ATAPI_DMA)) {
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u8 host_stat;
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host_stat = ap->ops->bmdma_status(ap);
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/* BMDMA controllers indicate host bus error by
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* setting DMA_ERR bit and timing out. As it wasn't
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* really a timeout event, adjust error mask and
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* cancel frozen state.
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*/
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if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
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qc->err_mask = AC_ERR_HOST_BUS;
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thaw = 1;
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}
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ap->ops->bmdma_stop(qc);
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}
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ata_altstatus(ap);
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ata_chk_status(ap);
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ap->ops->irq_clear(ap);
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spin_unlock_irqrestore(ap->lock, flags);
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if (thaw)
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ata_eh_thaw_port(ap);
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/* PIO and DMA engines have been stopped, perform recovery */
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ata_do_eh(ap, prereset, softreset, hardreset, postreset);
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}
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|
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/**
|
|
* ata_bmdma_error_handler - Stock error handler for BMDMA controller
|
|
* @ap: port to handle error for
|
|
*
|
|
* Stock error handler for BMDMA controller.
|
|
*
|
|
* LOCKING:
|
|
* Kernel thread context (may sleep)
|
|
*/
|
|
void ata_bmdma_error_handler(struct ata_port *ap)
|
|
{
|
|
ata_reset_fn_t hardreset;
|
|
|
|
hardreset = NULL;
|
|
if (sata_scr_valid(ap))
|
|
hardreset = sata_std_hardreset;
|
|
|
|
ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
|
|
ata_std_postreset);
|
|
}
|
|
|
|
/**
|
|
* ata_bmdma_post_internal_cmd - Stock post_internal_cmd for
|
|
* BMDMA controller
|
|
* @qc: internal command to clean up
|
|
*
|
|
* LOCKING:
|
|
* Kernel thread context (may sleep)
|
|
*/
|
|
void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
|
|
{
|
|
if (qc->ap->ioaddr.bmdma_addr)
|
|
ata_bmdma_stop(qc);
|
|
}
|
|
|
|
/**
|
|
* ata_sff_port_start - Set port up for dma.
|
|
* @ap: Port to initialize
|
|
*
|
|
* Called just after data structures for each port are
|
|
* initialized. Allocates space for PRD table if the device
|
|
* is DMA capable SFF.
|
|
*
|
|
* May be used as the port_start() entry in ata_port_operations.
|
|
*
|
|
* LOCKING:
|
|
* Inherited from caller.
|
|
*/
|
|
|
|
int ata_sff_port_start(struct ata_port *ap)
|
|
{
|
|
if (ap->ioaddr.bmdma_addr)
|
|
return ata_port_start(ap);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PCI
|
|
|
|
static int ata_resources_present(struct pci_dev *pdev, int port)
|
|
{
|
|
int i;
|
|
|
|
/* Check the PCI resources for this channel are enabled */
|
|
port = port * 2;
|
|
for (i = 0; i < 2; i ++) {
|
|
if (pci_resource_start(pdev, port + i) == 0 ||
|
|
pci_resource_len(pdev, port + i) == 0)
|
|
return 0;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
/**
|
|
* ata_pci_init_bmdma - acquire PCI BMDMA resources and init ATA host
|
|
* @host: target ATA host
|
|
*
|
|
* Acquire PCI BMDMA resources and initialize @host accordingly.
|
|
*
|
|
* LOCKING:
|
|
* Inherited from calling layer (may sleep).
|
|
*
|
|
* RETURNS:
|
|
* 0 on success, -errno otherwise.
|
|
*/
|
|
int ata_pci_init_bmdma(struct ata_host *host)
|
|
{
|
|
struct device *gdev = host->dev;
|
|
struct pci_dev *pdev = to_pci_dev(gdev);
|
|
int i, rc;
|
|
|
|
/* No BAR4 allocation: No DMA */
|
|
if (pci_resource_start(pdev, 4) == 0)
|
|
return 0;
|
|
|
|
/* TODO: If we get no DMA mask we should fall back to PIO */
|
|
rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
|
|
if (rc)
|
|
return rc;
|
|
rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
|
|
if (rc)
|
|
return rc;
|
|
|
|
/* request and iomap DMA region */
|
|
rc = pcim_iomap_regions(pdev, 1 << 4, DRV_NAME);
|
|
if (rc) {
|
|
dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n");
|
|
return -ENOMEM;
|
|
}
|
|
host->iomap = pcim_iomap_table(pdev);
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
struct ata_port *ap = host->ports[i];
|
|
void __iomem *bmdma = host->iomap[4] + 8 * i;
|
|
|
|
if (ata_port_is_dummy(ap))
|
|
continue;
|
|
|
|
ap->ioaddr.bmdma_addr = bmdma;
|
|
if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
|
|
(ioread8(bmdma + 2) & 0x80))
|
|
host->flags |= ATA_HOST_SIMPLEX;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* ata_pci_init_sff_host - acquire native PCI ATA resources and init host
|
|
* @host: target ATA host
|
|
*
|
|
* Acquire native PCI ATA resources for @host and initialize the
|
|
* first two ports of @host accordingly. Ports marked dummy are
|
|
* skipped and allocation failure makes the port dummy.
|
|
*
|
|
* Note that native PCI resources are valid even for legacy hosts
|
|
* as we fix up pdev resources array early in boot, so this
|
|
* function can be used for both native and legacy SFF hosts.
|
|
*
|
|
* LOCKING:
|
|
* Inherited from calling layer (may sleep).
|
|
*
|
|
* RETURNS:
|
|
* 0 if at least one port is initialized, -ENODEV if no port is
|
|
* available.
|
|
*/
|
|
int ata_pci_init_sff_host(struct ata_host *host)
|
|
{
|
|
struct device *gdev = host->dev;
|
|
struct pci_dev *pdev = to_pci_dev(gdev);
|
|
unsigned int mask = 0;
|
|
int i, rc;
|
|
|
|
/* request, iomap BARs and init port addresses accordingly */
|
|
for (i = 0; i < 2; i++) {
|
|
struct ata_port *ap = host->ports[i];
|
|
int base = i * 2;
|
|
void __iomem * const *iomap;
|
|
|
|
if (ata_port_is_dummy(ap))
|
|
continue;
|
|
|
|
/* Discard disabled ports. Some controllers show
|
|
* their unused channels this way. Disabled ports are
|
|
* made dummy.
|
|
*/
|
|
if (!ata_resources_present(pdev, i)) {
|
|
ap->ops = &ata_dummy_port_ops;
|
|
continue;
|
|
}
|
|
|
|
rc = pcim_iomap_regions(pdev, 0x3 << base, DRV_NAME);
|
|
if (rc) {
|
|
dev_printk(KERN_WARNING, gdev,
|
|
"failed to request/iomap BARs for port %d "
|
|
"(errno=%d)\n", i, rc);
|
|
if (rc == -EBUSY)
|
|
pcim_pin_device(pdev);
|
|
ap->ops = &ata_dummy_port_ops;
|
|
continue;
|
|
}
|
|
host->iomap = iomap = pcim_iomap_table(pdev);
|
|
|
|
ap->ioaddr.cmd_addr = iomap[base];
|
|
ap->ioaddr.altstatus_addr =
|
|
ap->ioaddr.ctl_addr = (void __iomem *)
|
|
((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
|
|
ata_std_ports(&ap->ioaddr);
|
|
|
|
mask |= 1 << i;
|
|
}
|
|
|
|
if (!mask) {
|
|
dev_printk(KERN_ERR, gdev, "no available native port\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* ata_pci_prepare_sff_host - helper to prepare native PCI ATA host
|
|
* @pdev: target PCI device
|
|
* @ppi: array of port_info, must be enough for two ports
|
|
* @r_host: out argument for the initialized ATA host
|
|
*
|
|
* Helper to allocate ATA host for @pdev, acquire all native PCI
|
|
* resources and initialize it accordingly in one go.
|
|
*
|
|
* LOCKING:
|
|
* Inherited from calling layer (may sleep).
|
|
*
|
|
* RETURNS:
|
|
* 0 on success, -errno otherwise.
|
|
*/
|
|
int ata_pci_prepare_sff_host(struct pci_dev *pdev,
|
|
const struct ata_port_info * const * ppi,
|
|
struct ata_host **r_host)
|
|
{
|
|
struct ata_host *host;
|
|
int rc;
|
|
|
|
if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
|
|
return -ENOMEM;
|
|
|
|
host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
|
|
if (!host) {
|
|
dev_printk(KERN_ERR, &pdev->dev,
|
|
"failed to allocate ATA host\n");
|
|
rc = -ENOMEM;
|
|
goto err_out;
|
|
}
|
|
|
|
rc = ata_pci_init_sff_host(host);
|
|
if (rc)
|
|
goto err_out;
|
|
|
|
/* init DMA related stuff */
|
|
rc = ata_pci_init_bmdma(host);
|
|
if (rc)
|
|
goto err_bmdma;
|
|
|
|
devres_remove_group(&pdev->dev, NULL);
|
|
*r_host = host;
|
|
return 0;
|
|
|
|
err_bmdma:
|
|
/* This is necessary because PCI and iomap resources are
|
|
* merged and releasing the top group won't release the
|
|
* acquired resources if some of those have been acquired
|
|
* before entering this function.
|
|
*/
|
|
pcim_iounmap_regions(pdev, 0xf);
|
|
err_out:
|
|
devres_release_group(&pdev->dev, NULL);
|
|
return rc;
|
|
}
|
|
|
|
/**
|
|
* ata_pci_init_one - Initialize/register PCI IDE host controller
|
|
* @pdev: Controller to be initialized
|
|
* @ppi: array of port_info, must be enough for two ports
|
|
*
|
|
* This is a helper function which can be called from a driver's
|
|
* xxx_init_one() probe function if the hardware uses traditional
|
|
* IDE taskfile registers.
|
|
*
|
|
* This function calls pci_enable_device(), reserves its register
|
|
* regions, sets the dma mask, enables bus master mode, and calls
|
|
* ata_device_add()
|
|
*
|
|
* ASSUMPTION:
|
|
* Nobody makes a single channel controller that appears solely as
|
|
* the secondary legacy port on PCI.
|
|
*
|
|
* LOCKING:
|
|
* Inherited from PCI layer (may sleep).
|
|
*
|
|
* RETURNS:
|
|
* Zero on success, negative on errno-based value on error.
|
|
*/
|
|
int ata_pci_init_one(struct pci_dev *pdev,
|
|
const struct ata_port_info * const * ppi)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
const struct ata_port_info *pi = NULL;
|
|
struct ata_host *host = NULL;
|
|
u8 mask;
|
|
int legacy_mode = 0;
|
|
int i, rc;
|
|
|
|
DPRINTK("ENTER\n");
|
|
|
|
/* look up the first valid port_info */
|
|
for (i = 0; i < 2 && ppi[i]; i++) {
|
|
if (ppi[i]->port_ops != &ata_dummy_port_ops) {
|
|
pi = ppi[i];
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!pi) {
|
|
dev_printk(KERN_ERR, &pdev->dev,
|
|
"no valid port_info specified\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (!devres_open_group(dev, NULL, GFP_KERNEL))
|
|
return -ENOMEM;
|
|
|
|
/* FIXME: Really for ATA it isn't safe because the device may be
|
|
multi-purpose and we want to leave it alone if it was already
|
|
enabled. Secondly for shared use as Arjan says we want refcounting
|
|
|
|
Checking dev->is_enabled is insufficient as this is not set at
|
|
boot for the primary video which is BIOS enabled
|
|
*/
|
|
|
|
rc = pcim_enable_device(pdev);
|
|
if (rc)
|
|
goto err_out;
|
|
|
|
if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
|
|
u8 tmp8;
|
|
|
|
/* TODO: What if one channel is in native mode ... */
|
|
pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
|
|
mask = (1 << 2) | (1 << 0);
|
|
if ((tmp8 & mask) != mask)
|
|
legacy_mode = 1;
|
|
#if defined(CONFIG_NO_ATA_LEGACY)
|
|
/* Some platforms with PCI limits cannot address compat
|
|
port space. In that case we punt if their firmware has
|
|
left a device in compatibility mode */
|
|
if (legacy_mode) {
|
|
printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n");
|
|
rc = -EOPNOTSUPP;
|
|
goto err_out;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/* prepare host */
|
|
rc = ata_pci_prepare_sff_host(pdev, ppi, &host);
|
|
if (rc)
|
|
goto err_out;
|
|
|
|
pci_set_master(pdev);
|
|
|
|
/* start host and request IRQ */
|
|
rc = ata_host_start(host);
|
|
if (rc)
|
|
goto err_out;
|
|
|
|
if (!legacy_mode) {
|
|
rc = devm_request_irq(dev, pdev->irq, pi->port_ops->irq_handler,
|
|
IRQF_SHARED, DRV_NAME, host);
|
|
if (rc)
|
|
goto err_out;
|
|
host->irq = pdev->irq;
|
|
} else {
|
|
if (!ata_port_is_dummy(host->ports[0])) {
|
|
host->irq = ATA_PRIMARY_IRQ(pdev);
|
|
rc = devm_request_irq(dev, host->irq,
|
|
pi->port_ops->irq_handler,
|
|
IRQF_SHARED, DRV_NAME, host);
|
|
if (rc)
|
|
goto err_out;
|
|
}
|
|
|
|
if (!ata_port_is_dummy(host->ports[1])) {
|
|
host->irq2 = ATA_SECONDARY_IRQ(pdev);
|
|
rc = devm_request_irq(dev, host->irq2,
|
|
pi->port_ops->irq_handler,
|
|
IRQF_SHARED, DRV_NAME, host);
|
|
if (rc)
|
|
goto err_out;
|
|
}
|
|
}
|
|
|
|
/* register */
|
|
rc = ata_host_register(host, pi->sht);
|
|
if (rc)
|
|
goto err_out;
|
|
|
|
devres_remove_group(dev, NULL);
|
|
return 0;
|
|
|
|
err_out:
|
|
devres_release_group(dev, NULL);
|
|
return rc;
|
|
}
|
|
|
|
/**
|
|
* ata_pci_clear_simplex - attempt to kick device out of simplex
|
|
* @pdev: PCI device
|
|
*
|
|
* Some PCI ATA devices report simplex mode but in fact can be told to
|
|
* enter non simplex mode. This implements the neccessary logic to
|
|
* perform the task on such devices. Calling it on other devices will
|
|
* have -undefined- behaviour.
|
|
*/
|
|
|
|
int ata_pci_clear_simplex(struct pci_dev *pdev)
|
|
{
|
|
unsigned long bmdma = pci_resource_start(pdev, 4);
|
|
u8 simplex;
|
|
|
|
if (bmdma == 0)
|
|
return -ENOENT;
|
|
|
|
simplex = inb(bmdma + 0x02);
|
|
outb(simplex & 0x60, bmdma + 0x02);
|
|
simplex = inb(bmdma + 0x02);
|
|
if (simplex & 0x80)
|
|
return -EOPNOTSUPP;
|
|
return 0;
|
|
}
|
|
|
|
unsigned long ata_pci_default_filter(struct ata_device *adev, unsigned long xfer_mask)
|
|
{
|
|
/* Filter out DMA modes if the device has been configured by
|
|
the BIOS as PIO only */
|
|
|
|
if (adev->ap->ioaddr.bmdma_addr == 0)
|
|
xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
|
|
return xfer_mask;
|
|
}
|
|
|
|
#endif /* CONFIG_PCI */
|
|
|