forked from Minki/linux
1846e3f9e7
Enable realtime memory utilization report on Vega20. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
306 lines
10 KiB
C
306 lines
10 KiB
C
/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __KGD_PP_INTERFACE_H__
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#define __KGD_PP_INTERFACE_H__
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extern const struct amdgpu_ip_block_version pp_smu_ip_block;
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struct amd_vce_state {
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/* vce clocks */
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u32 evclk;
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u32 ecclk;
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/* gpu clocks */
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u32 sclk;
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u32 mclk;
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u8 clk_idx;
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u8 pstate;
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};
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enum amd_dpm_forced_level {
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AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
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AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
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AMD_DPM_FORCED_LEVEL_LOW = 0x4,
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AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
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AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
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AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
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AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
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AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
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AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
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};
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enum amd_pm_state_type {
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/* not used for dpm */
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POWER_STATE_TYPE_DEFAULT,
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POWER_STATE_TYPE_POWERSAVE,
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/* user selectable states */
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POWER_STATE_TYPE_BATTERY,
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POWER_STATE_TYPE_BALANCED,
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POWER_STATE_TYPE_PERFORMANCE,
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/* internal states */
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POWER_STATE_TYPE_INTERNAL_UVD,
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POWER_STATE_TYPE_INTERNAL_UVD_SD,
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POWER_STATE_TYPE_INTERNAL_UVD_HD,
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POWER_STATE_TYPE_INTERNAL_UVD_HD2,
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POWER_STATE_TYPE_INTERNAL_UVD_MVC,
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POWER_STATE_TYPE_INTERNAL_BOOT,
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POWER_STATE_TYPE_INTERNAL_THERMAL,
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POWER_STATE_TYPE_INTERNAL_ACPI,
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POWER_STATE_TYPE_INTERNAL_ULV,
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POWER_STATE_TYPE_INTERNAL_3DPERF,
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};
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#define AMD_MAX_VCE_LEVELS 6
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enum amd_vce_level {
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AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
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AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
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AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
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AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
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AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
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AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
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};
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enum amd_fan_ctrl_mode {
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AMD_FAN_CTRL_NONE = 0,
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AMD_FAN_CTRL_MANUAL = 1,
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AMD_FAN_CTRL_AUTO = 2,
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};
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enum pp_clock_type {
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PP_SCLK,
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PP_MCLK,
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PP_PCIE,
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PP_SOCCLK,
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PP_FCLK,
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PP_DCEFCLK,
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OD_SCLK,
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OD_MCLK,
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OD_VDDC_CURVE,
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OD_RANGE,
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};
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enum amd_pp_sensors {
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AMDGPU_PP_SENSOR_GFX_SCLK = 0,
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AMDGPU_PP_SENSOR_VDDNB,
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AMDGPU_PP_SENSOR_VDDGFX,
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AMDGPU_PP_SENSOR_UVD_VCLK,
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AMDGPU_PP_SENSOR_UVD_DCLK,
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AMDGPU_PP_SENSOR_VCE_ECCLK,
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AMDGPU_PP_SENSOR_GPU_LOAD,
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AMDGPU_PP_SENSOR_MEM_LOAD,
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AMDGPU_PP_SENSOR_GFX_MCLK,
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AMDGPU_PP_SENSOR_GPU_TEMP,
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AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
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AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
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AMDGPU_PP_SENSOR_MEM_TEMP,
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AMDGPU_PP_SENSOR_VCE_POWER,
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AMDGPU_PP_SENSOR_UVD_POWER,
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AMDGPU_PP_SENSOR_GPU_POWER,
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AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
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AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
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AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
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AMDGPU_PP_SENSOR_MIN_FAN_RPM,
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AMDGPU_PP_SENSOR_MAX_FAN_RPM,
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};
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enum amd_pp_task {
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AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
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AMD_PP_TASK_ENABLE_USER_STATE,
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AMD_PP_TASK_READJUST_POWER_STATE,
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AMD_PP_TASK_COMPLETE_INIT,
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AMD_PP_TASK_MAX
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};
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enum PP_SMC_POWER_PROFILE {
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PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
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PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
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PP_SMC_POWER_PROFILE_POWERSAVING = 0x2,
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PP_SMC_POWER_PROFILE_VIDEO = 0x3,
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PP_SMC_POWER_PROFILE_VR = 0x4,
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PP_SMC_POWER_PROFILE_COMPUTE = 0x5,
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PP_SMC_POWER_PROFILE_CUSTOM = 0x6,
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};
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enum {
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PP_GROUP_UNKNOWN = 0,
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PP_GROUP_GFX = 1,
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PP_GROUP_SYS,
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PP_GROUP_MAX
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};
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enum PP_OD_DPM_TABLE_COMMAND {
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PP_OD_EDIT_SCLK_VDDC_TABLE,
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PP_OD_EDIT_MCLK_VDDC_TABLE,
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PP_OD_EDIT_VDDC_CURVE,
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PP_OD_RESTORE_DEFAULT_TABLE,
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PP_OD_COMMIT_DPM_TABLE
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};
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struct pp_states_info {
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uint32_t nums;
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uint32_t states[16];
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};
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enum PP_HWMON_TEMP {
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PP_TEMP_EDGE = 0,
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PP_TEMP_JUNCTION,
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PP_TEMP_MEM,
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PP_TEMP_MAX
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};
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#define PP_GROUP_MASK 0xF0000000
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#define PP_GROUP_SHIFT 28
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#define PP_BLOCK_MASK 0x0FFFFF00
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#define PP_BLOCK_SHIFT 8
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#define PP_BLOCK_GFX_CG 0x01
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#define PP_BLOCK_GFX_MG 0x02
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#define PP_BLOCK_GFX_3D 0x04
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#define PP_BLOCK_GFX_RLC 0x08
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#define PP_BLOCK_GFX_CP 0x10
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#define PP_BLOCK_SYS_BIF 0x01
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#define PP_BLOCK_SYS_MC 0x02
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#define PP_BLOCK_SYS_ROM 0x04
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#define PP_BLOCK_SYS_DRM 0x08
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#define PP_BLOCK_SYS_HDP 0x10
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#define PP_BLOCK_SYS_SDMA 0x20
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#define PP_STATE_MASK 0x0000000F
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#define PP_STATE_SHIFT 0
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#define PP_STATE_SUPPORT_MASK 0x000000F0
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#define PP_STATE_SUPPORT_SHIFT 0
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#define PP_STATE_CG 0x01
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#define PP_STATE_LS 0x02
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#define PP_STATE_DS 0x04
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#define PP_STATE_SD 0x08
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#define PP_STATE_SUPPORT_CG 0x10
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#define PP_STATE_SUPPORT_LS 0x20
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#define PP_STATE_SUPPORT_DS 0x40
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#define PP_STATE_SUPPORT_SD 0x80
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#define PP_CG_MSG_ID(group, block, support, state) \
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((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
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(support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
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struct seq_file;
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enum amd_pp_clock_type;
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struct amd_pp_simple_clock_info;
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struct amd_pp_display_configuration;
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struct amd_pp_clock_info;
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struct pp_display_clock_request;
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struct pp_clock_levels_with_voltage;
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struct pp_clock_levels_with_latency;
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struct amd_pp_clocks;
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struct amd_pm_funcs {
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/* export for dpm on ci and si */
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int (*pre_set_power_state)(void *handle);
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int (*set_power_state)(void *handle);
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void (*post_set_power_state)(void *handle);
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void (*display_configuration_changed)(void *handle);
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void (*print_power_state)(void *handle, void *ps);
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bool (*vblank_too_short)(void *handle);
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void (*enable_bapm)(void *handle, bool enable);
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int (*check_state_equal)(void *handle,
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void *cps,
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void *rps,
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bool *equal);
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/* export for sysfs */
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void (*set_fan_control_mode)(void *handle, u32 mode);
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u32 (*get_fan_control_mode)(void *handle);
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int (*set_fan_speed_percent)(void *handle, u32 speed);
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int (*get_fan_speed_percent)(void *handle, u32 *speed);
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int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
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int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
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int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
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int (*get_sclk_od)(void *handle);
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int (*set_sclk_od)(void *handle, uint32_t value);
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int (*get_mclk_od)(void *handle);
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int (*set_mclk_od)(void *handle, uint32_t value);
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int (*read_sensor)(void *handle, int idx, void *value, int *size);
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enum amd_dpm_forced_level (*get_performance_level)(void *handle);
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enum amd_pm_state_type (*get_current_power_state)(void *handle);
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int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
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int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
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int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
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int (*get_pp_table)(void *handle, char **table);
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int (*set_pp_table)(void *handle, const char *buf, size_t size);
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void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
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int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
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/* export to amdgpu */
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struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
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int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
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enum amd_pm_state_type *user_state);
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int (*load_firmware)(void *handle);
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int (*wait_for_fw_loading_complete)(void *handle);
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int (*set_powergating_by_smu)(void *handle,
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uint32_t block_type, bool gate);
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int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
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int (*set_power_limit)(void *handle, uint32_t n);
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int (*get_power_limit)(void *handle, uint32_t *limit, bool default_limit);
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int (*get_power_profile_mode)(void *handle, char *buf);
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int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
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int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
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/* export to DC */
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u32 (*get_sclk)(void *handle, bool low);
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u32 (*get_mclk)(void *handle, bool low);
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int (*display_configuration_change)(void *handle,
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const struct amd_pp_display_configuration *input);
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int (*get_display_power_level)(void *handle,
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struct amd_pp_simple_clock_info *output);
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int (*get_current_clocks)(void *handle,
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struct amd_pp_clock_info *clocks);
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int (*get_clock_by_type)(void *handle,
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enum amd_pp_clock_type type,
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struct amd_pp_clocks *clocks);
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int (*get_clock_by_type_with_latency)(void *handle,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_latency *clocks);
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int (*get_clock_by_type_with_voltage)(void *handle,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_voltage *clocks);
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int (*set_watermarks_for_clocks_ranges)(void *handle,
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void *clock_ranges);
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int (*display_clock_voltage_request)(void *handle,
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struct pp_display_clock_request *clock);
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int (*get_display_mode_validation_clocks)(void *handle,
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struct amd_pp_simple_clock_info *clocks);
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int (*notify_smu_enable_pwe)(void *handle);
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int (*enable_mgpu_fan_boost)(void *handle);
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int (*set_active_display_count)(void *handle, uint32_t count);
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int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
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int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
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int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
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int (*get_asic_baco_capability)(void *handle, bool *cap);
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int (*get_asic_baco_state)(void *handle, int *state);
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int (*set_asic_baco_state)(void *handle, int state);
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int (*get_ppfeature_status)(void *handle, char *buf);
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int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
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};
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#endif
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