forked from Minki/linux
0c9d70d724
This patch adds descriptions for new properties of the device tree
binding for the ARM SMMU architecture. These properties control
arm-smmu driver options.
Cc: Grant Likely <grant.likely@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com>
[will: removed device isolation property, as this has been dropped and
fixed up spacing in documentation]
Signed-off-by: Will Deacon <will.deacon@arm.com>
77 lines
3.0 KiB
Plaintext
77 lines
3.0 KiB
Plaintext
* ARM System MMU Architecture Implementation
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ARM SoCs may contain an implementation of the ARM System Memory
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Management Unit Architecture, which can be used to provide 1 or 2 stages
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of address translation to bus masters external to the CPU.
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The SMMU may also raise interrupts in response to various fault
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conditions.
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** System MMU required properties:
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- compatible : Should be one of:
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"arm,smmu-v1"
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"arm,smmu-v2"
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"arm,mmu-400"
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"arm,mmu-500"
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depending on the particular implementation and/or the
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version of the architecture implemented.
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- reg : Base address and size of the SMMU.
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- #global-interrupts : The number of global interrupts exposed by the
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device.
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- interrupts : Interrupt list, with the first #global-irqs entries
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corresponding to the global interrupts and any
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following entries corresponding to context interrupts,
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specified in order of their indexing by the SMMU.
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For SMMUv2 implementations, there must be exactly one
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interrupt per context bank. In the case of a single,
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combined interrupt, it must be listed multiple times.
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- mmu-masters : A list of phandles to device nodes representing bus
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masters for which the SMMU can provide a translation
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and their corresponding StreamIDs (see example below).
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Each device node linked from this list must have a
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"#stream-id-cells" property, indicating the number of
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StreamIDs associated with it.
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** System MMU optional properties:
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- smmu-parent : When multiple SMMUs are chained together, this
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property can be used to provide a phandle to the
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parent SMMU (that is the next SMMU on the path going
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from the mmu-masters towards memory) node for this
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SMMU.
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- calxeda,smmu-secure-config-access : Enable proper handling of buggy
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implementations that always use secure access to
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SMMU configuration registers. In this case non-secure
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aliases of secure registers have to be used during
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SMMU configuration.
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Example:
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smmu {
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compatible = "arm,smmu-v1";
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reg = <0xba5e0000 0x10000>;
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#global-interrupts = <2>;
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interrupts = <0 32 4>,
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<0 33 4>,
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<0 34 4>, /* This is the first context interrupt */
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<0 35 4>,
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<0 36 4>,
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<0 37 4>;
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/*
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* Two DMA controllers, the first with two StreamIDs (0xd01d
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* and 0xd01e) and the second with only one (0xd11c).
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*/
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mmu-masters = <&dma0 0xd01d 0xd01e>,
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<&dma1 0xd11c>;
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};
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