Guo Ren 0c8a32eed1 csky: Add memory layout 2.5G(user):1.5G(kernel) ... There are two ways for translating va to pa for csky: - Use TLB(Translate Lookup Buffer) and PTW (Page Table Walk) - Use SSEG0/1 (Simple Segment Mapping) We use tlb mapping 0-2G and 3G-4G virtual address area and SSEG0/1 are for 2G-2.5G and 2.5G-3G translation. We could disable SSEG0 to use 2G-2.5G as TLB user mapping. Signed-off-by: Guo Ren <guoren@linux.alibaba.com>		2021-01-12 09:52:40 +08:00
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cacheflush.h	csky: Add flush_icache_mm to defer flush icache all	2020-02-21 15:43:24 +08:00
ckmmu.h	csky: Add memory layout 2.5G(user):1.5G(kernel)	2021-01-12 09:52:40 +08:00
elf.h	csky: ELF and module probe	2018-10-26 00:54:23 +08:00
entry.h	csky: Add memory layout 2.5G(user):1.5G(kernel)	2021-01-12 09:52:40 +08:00
fpu.h	csky: Fixup init_fpu compile warning with __init	2020-03-08 20:55:14 +08:00
page.h	csky: MMU and page table management	2018-10-25 23:36:19 +08:00
pgtable-bits.h	csky: fixup abiv2 mmap(... O_SYNC) failed.	2018-12-31 10:56:45 +08:00
reg_ops.h	csky: Misc headers	2018-10-26 00:54:26 +08:00
regdef.h	csky: Add perf_arch_fetch_caller_regs support	2019-04-22 13:44:57 +08:00
string.h	csky: Library functions	2018-10-26 00:54:24 +08:00
switch_context.h	csky: fixup save hi,lo,dspcr regs in switch_stack.	2018-12-31 22:57:27 +08:00
vdso.h	csky: VDSO and rt_sigreturn	2018-10-26 00:54:22 +08:00