forked from Minki/linux
f03defe0b7
Rather than casting and shifting. Fixes sparse cast warnings. Reviewed-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
309 lines
8.8 KiB
C
309 lines
8.8 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Author: Huang Rui
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*
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*/
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#include <linux/firmware.h>
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#include "amdgpu.h"
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#include "amdgpu_psp.h"
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#include "amdgpu_ucode.h"
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#include "soc15_common.h"
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#include "psp_v10_0.h"
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#include "vega10/soc15ip.h"
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#include "raven1/MP/mp_10_0_offset.h"
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#include "raven1/GC/gc_9_1_offset.h"
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#include "raven1/SDMA0/sdma0_4_1_offset.h"
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static int
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psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
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{
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switch(ucode->ucode_id) {
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case AMDGPU_UCODE_ID_SDMA0:
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*type = GFX_FW_TYPE_SDMA0;
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break;
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case AMDGPU_UCODE_ID_SDMA1:
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*type = GFX_FW_TYPE_SDMA1;
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break;
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case AMDGPU_UCODE_ID_CP_CE:
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*type = GFX_FW_TYPE_CP_CE;
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break;
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case AMDGPU_UCODE_ID_CP_PFP:
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*type = GFX_FW_TYPE_CP_PFP;
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break;
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case AMDGPU_UCODE_ID_CP_ME:
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*type = GFX_FW_TYPE_CP_ME;
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break;
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case AMDGPU_UCODE_ID_CP_MEC1:
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*type = GFX_FW_TYPE_CP_MEC;
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break;
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case AMDGPU_UCODE_ID_CP_MEC1_JT:
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*type = GFX_FW_TYPE_CP_MEC_ME1;
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break;
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case AMDGPU_UCODE_ID_CP_MEC2:
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*type = GFX_FW_TYPE_CP_MEC;
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break;
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case AMDGPU_UCODE_ID_CP_MEC2_JT:
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*type = GFX_FW_TYPE_CP_MEC_ME2;
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break;
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case AMDGPU_UCODE_ID_RLC_G:
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*type = GFX_FW_TYPE_RLC_G;
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break;
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case AMDGPU_UCODE_ID_SMC:
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*type = GFX_FW_TYPE_SMU;
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break;
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case AMDGPU_UCODE_ID_UVD:
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*type = GFX_FW_TYPE_UVD;
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break;
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case AMDGPU_UCODE_ID_VCE:
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*type = GFX_FW_TYPE_VCE;
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break;
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case AMDGPU_UCODE_ID_MAXIMUM:
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default:
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return -EINVAL;
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}
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return 0;
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}
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int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd)
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{
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int ret;
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uint64_t fw_mem_mc_addr = ucode->mc_addr;
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struct common_firmware_header *header;
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memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
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header = (struct common_firmware_header *)ucode->fw;
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cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
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cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
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cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
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cmd->cmd.cmd_load_ip_fw.fw_size = le32_to_cpu(header->ucode_size_bytes);
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ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
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if (ret)
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DRM_ERROR("Unknown firmware type\n");
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return ret;
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}
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int psp_v10_0_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
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{
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int ret = 0;
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unsigned int psp_ring_reg = 0;
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struct psp_ring *ring;
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struct amdgpu_device *adev = psp->adev;
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ring = &psp->km_ring;
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ring->ring_type = ring_type;
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/* allocate 4k Page of Local Frame Buffer memory for ring */
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ring->ring_size = 0x1000;
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ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&adev->firmware.rbuf,
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&ring->ring_mem_mc_addr,
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(void **)&ring->ring_mem);
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if (ret) {
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ring->ring_size = 0;
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return ret;
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}
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/* Write low address of the ring to C2PMSG_69 */
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psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
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/* Write high address of the ring to C2PMSG_70 */
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psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
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/* Write size of ring to C2PMSG_71 */
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psp_ring_reg = ring->ring_size;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
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/* Write the ring initialization command to C2PMSG_64 */
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psp_ring_reg = ring_type;
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psp_ring_reg = psp_ring_reg << 16;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
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/* Wait for response flag (bit 31) in C2PMSG_64 */
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psp_ring_reg = 0;
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while ((psp_ring_reg & 0x80000000) == 0) {
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psp_ring_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64);
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}
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return 0;
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}
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int psp_v10_0_cmd_submit(struct psp_context *psp,
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struct amdgpu_firmware_info *ucode,
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uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
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int index)
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{
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unsigned int psp_write_ptr_reg = 0;
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struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
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struct psp_ring *ring = &psp->km_ring;
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struct amdgpu_device *adev = psp->adev;
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/* KM (GPCOM) prepare write pointer */
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psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
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/* Update KM RB frame pointer to new frame */
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if ((psp_write_ptr_reg % ring->ring_size) == 0)
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write_frame = ring->ring_mem;
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else
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write_frame = ring->ring_mem + (psp_write_ptr_reg / (sizeof(struct psp_gfx_rb_frame) / 4));
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/* Update KM RB frame */
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write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
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write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
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write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
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write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
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write_frame->fence_value = index;
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/* Update the write Pointer in DWORDs */
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psp_write_ptr_reg += sizeof(struct psp_gfx_rb_frame) / 4;
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psp_write_ptr_reg = (psp_write_ptr_reg >= ring->ring_size) ? 0 : psp_write_ptr_reg;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
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return 0;
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}
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static int
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psp_v10_0_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
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unsigned int *sram_data_reg_offset,
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enum AMDGPU_UCODE_ID ucode_id)
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{
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int ret = 0;
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switch(ucode_id) {
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/* TODO: needs to confirm */
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#if 0
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case AMDGPU_UCODE_ID_SMC:
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*sram_offset = 0;
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*sram_addr_reg_offset = 0;
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*sram_data_reg_offset = 0;
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break;
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#endif
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case AMDGPU_UCODE_ID_CP_CE:
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*sram_offset = 0x0;
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*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
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*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
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break;
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case AMDGPU_UCODE_ID_CP_PFP:
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*sram_offset = 0x0;
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*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
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*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
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break;
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case AMDGPU_UCODE_ID_CP_ME:
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*sram_offset = 0x0;
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*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
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*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
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break;
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case AMDGPU_UCODE_ID_CP_MEC1:
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*sram_offset = 0x10000;
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*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
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*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
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break;
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case AMDGPU_UCODE_ID_CP_MEC2:
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*sram_offset = 0x10000;
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*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
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*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
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break;
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case AMDGPU_UCODE_ID_RLC_G:
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*sram_offset = 0x2000;
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*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
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*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
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break;
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case AMDGPU_UCODE_ID_SDMA0:
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*sram_offset = 0x0;
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*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
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*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
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break;
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/* TODO: needs to confirm */
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#if 0
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case AMDGPU_UCODE_ID_SDMA1:
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*sram_offset = ;
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*sram_addr_reg_offset = ;
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break;
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case AMDGPU_UCODE_ID_UVD:
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*sram_offset = ;
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*sram_addr_reg_offset = ;
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break;
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case AMDGPU_UCODE_ID_VCE:
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*sram_offset = ;
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*sram_addr_reg_offset = ;
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break;
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#endif
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case AMDGPU_UCODE_ID_MAXIMUM:
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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bool psp_v10_0_compare_sram_data(struct psp_context *psp,
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struct amdgpu_firmware_info *ucode,
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enum AMDGPU_UCODE_ID ucode_type)
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{
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int err = 0;
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unsigned int fw_sram_reg_val = 0;
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unsigned int fw_sram_addr_reg_offset = 0;
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unsigned int fw_sram_data_reg_offset = 0;
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unsigned int ucode_size;
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uint32_t *ucode_mem = NULL;
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struct amdgpu_device *adev = psp->adev;
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err = psp_v10_0_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset,
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&fw_sram_data_reg_offset, ucode_type);
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if (err)
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return false;
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WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
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ucode_size = ucode->ucode_size;
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ucode_mem = (uint32_t *)ucode->kaddr;
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while (!ucode_size) {
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fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
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if (*ucode_mem != fw_sram_reg_val)
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return false;
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ucode_mem++;
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/* 4 bytes */
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ucode_size -= 4;
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}
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return true;
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}
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