forked from Minki/linux
147 lines
3.8 KiB
C
147 lines
3.8 KiB
C
/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_bios.h"
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#include "nouveau_pm.h"
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struct nv50_pm_state {
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struct nouveau_pm_level *perflvl;
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struct pll_lims pll;
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enum pll_types type;
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int N, M, P;
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};
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int
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nv50_pm_clock_get(struct drm_device *dev, u32 id)
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{
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struct pll_lims pll;
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int P, N, M, ret;
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u32 reg0, reg1;
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ret = get_pll_limits(dev, id, &pll);
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if (ret)
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return ret;
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reg0 = nv_rd32(dev, pll.reg + 0);
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reg1 = nv_rd32(dev, pll.reg + 4);
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if ((reg0 & 0x80000000) == 0) {
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if (id == PLL_SHADER) {
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NV_DEBUG(dev, "Shader PLL is disabled. "
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"Shader clock is twice the core\n");
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ret = nv50_pm_clock_get(dev, PLL_CORE);
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if (ret > 0)
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return ret << 1;
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} else if (id == PLL_MEMORY) {
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NV_DEBUG(dev, "Memory PLL is disabled. "
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"Memory clock is equal to the ref_clk\n");
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return pll.refclk;
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}
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}
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P = (reg0 & 0x00070000) >> 16;
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N = (reg1 & 0x0000ff00) >> 8;
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M = (reg1 & 0x000000ff);
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return ((pll.refclk * N / M) >> P);
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}
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void *
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nv50_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl,
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u32 id, int khz)
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{
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struct nv50_pm_state *state;
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int dummy, ret;
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state = kzalloc(sizeof(*state), GFP_KERNEL);
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if (!state)
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return ERR_PTR(-ENOMEM);
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state->type = id;
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state->perflvl = perflvl;
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ret = get_pll_limits(dev, id, &state->pll);
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if (ret < 0) {
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kfree(state);
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return (ret == -ENOENT) ? NULL : ERR_PTR(ret);
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}
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ret = nv50_calc_pll(dev, &state->pll, khz, &state->N, &state->M,
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&dummy, &dummy, &state->P);
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if (ret < 0) {
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kfree(state);
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return ERR_PTR(ret);
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}
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return state;
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}
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void
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nv50_pm_clock_set(struct drm_device *dev, void *pre_state)
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{
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struct nv50_pm_state *state = pre_state;
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struct nouveau_pm_level *perflvl = state->perflvl;
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u32 reg = state->pll.reg, tmp;
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struct bit_entry BIT_M;
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u16 script;
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int N = state->N;
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int M = state->M;
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int P = state->P;
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if (state->type == PLL_MEMORY && perflvl->memscript &&
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bit_table(dev, 'M', &BIT_M) == 0 &&
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BIT_M.version == 1 && BIT_M.length >= 0x0b) {
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script = ROM16(BIT_M.data[0x05]);
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if (script)
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nouveau_bios_run_init_table(dev, script, NULL, -1);
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script = ROM16(BIT_M.data[0x07]);
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if (script)
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nouveau_bios_run_init_table(dev, script, NULL, -1);
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script = ROM16(BIT_M.data[0x09]);
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if (script)
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nouveau_bios_run_init_table(dev, script, NULL, -1);
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nouveau_bios_run_init_table(dev, perflvl->memscript, NULL, -1);
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}
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if (state->type == PLL_MEMORY) {
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nv_wr32(dev, 0x100210, 0);
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nv_wr32(dev, 0x1002dc, 1);
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}
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tmp = nv_rd32(dev, reg + 0) & 0xfff8ffff;
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tmp |= 0x80000000 | (P << 16);
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nv_wr32(dev, reg + 0, tmp);
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nv_wr32(dev, reg + 4, (N << 8) | M);
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if (state->type == PLL_MEMORY) {
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nv_wr32(dev, 0x1002dc, 0);
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nv_wr32(dev, 0x100210, 0x80000000);
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}
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kfree(state);
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}
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