linux/arch/riscv
Linus Torvalds 498574970f RISC-V Patches for the 6.1 Merge Window, Part 2
* A handful of DT updates for the PolarFire SOC.
 * A fix to correct the handling of write-only mappings.
 * m{vetndor,arcd,imp}id is now in /proc/cpuinfo
 * The SiFive L2 cache controller support has been refactored to also
   support L3 caches.
 
 There's also a handful of fixes, cleanups and improvements throughout
 the tree.
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Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull more RISC-V updates from Palmer Dabbelt:

 - DT updates for the PolarFire SOC

 - a fix to correct the handling of write-only mappings

 - m{vetndor,arcd,imp}id is now in /proc/cpuinfo

 - the SiFive L2 cache controller support has been refactored to also
   support L3 caches

 - misc fixes, cleanups and improvements throughout the tree

* tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (42 commits)
  MAINTAINERS: add RISC-V's patchwork
  RISC-V: Make port I/O string accessors actually work
  riscv: enable software resend of irqs
  RISC-V: Re-enable counter access from userspace
  riscv: vdso: fix NULL deference in vdso_join_timens() when vfork
  riscv: Add cache information in AUX vector
  soc: sifive: ccache: define the macro for the register shifts
  soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes
  soc: sifive: ccache: reduce printing on init
  soc: sifive: ccache: determine the cache level from dts
  soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.
  dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache
  riscv: check for kernel config option in t-head memory types errata
  riscv: use BIT() marco for cpufeature probing
  riscv: use BIT() macros in t-head errata init
  riscv: drop some idefs from CMO initialization
  riscv: cleanup svpbmt cpufeature probing
  riscv: Pass -mno-relax only on lld < 15.0.0
  RISC-V: Avoid dereferening NULL regs in die()
  dt-bindings: riscv: add new riscv,isa strings for emulators
  ...
2022-10-14 11:21:11 -07:00
..
boot RISC-V Patches for the 6.1 Merge Window, Part 2 2022-10-14 11:21:11 -07:00
configs riscv: enable CD-ROM file systems in defconfig 2022-08-25 17:01:09 -07:00
errata Merge patch series "Some style cleanups for recent extension additions" 2022-10-13 08:46:31 -07:00
include RISC-V Patches for the 6.1 Merge Window, Part 2 2022-10-14 11:21:11 -07:00
kernel RISC-V Patches for the 6.1 Merge Window, Part 2 2022-10-14 11:21:11 -07:00
kvm The first batch of KVM patches, mostly covering x86, which I 2022-10-09 09:39:55 -07:00
lib riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit 2022-08-10 14:06:31 -07:00
mm RISC-V Patches for the 6.1 Merge Window, Part 2 2022-10-14 11:21:11 -07:00
net bpf, riscv: Support riscv jit to provide bpf_line_info 2022-06-02 16:26:01 -07:00
purgatory riscv/purgatory: Omit use of bin2c 2022-08-11 09:32:34 -07:00
Kbuild riscv: move errata/ and kvm/ builds to arch/riscv/Kbuild 2022-06-01 22:26:32 -07:00
Kconfig RISC-V Patches for the 6.1 Merge Window, Part 2 2022-10-14 11:21:11 -07:00
Kconfig.debug RISC-V: Remove EARLY_PRINTK support 2018-12-17 10:23:46 -08:00
Kconfig.erratas riscv: make t-head erratas depend on MMU 2022-09-17 01:48:22 -07:00
Kconfig.socs riscv: Kconfig: Style cleanups 2022-06-30 19:26:16 -07:00
Makefile RISC-V Patches for the 6.1 Merge Window, Part 2 2022-10-14 11:21:11 -07:00