0b776d457b
As a result of atomic DPMS support, the various prepare/commit hooks get called in a way that msm dislikes. We were expecting prepare/commit to bracket a modeset, which is no longer the case. This was needed to hold various extra clk's (such as interface clks) on while we are touching registers, and in the case of mdp4 holding vblank enabled. The most straightforward way to deal with this, since we already have our own atomic_commit(), is to just handle prepare/commit internally to the driver (with some additional vfuncs for mdp4 vs mdp5), and switch everything over to instead use the new enable/disable hooks. It doesn't really change too much, despite the code motion. What used to be in the encoder/crtc dpms() fxns is split out into enable/disable. We should be able to drop our own enable-state tracking, as the atomic helpers should do this for us. But keeping that for the short term for extra debugging as atomic stablizes. Signed-off-by: Rob Clark <robdclark@gmail.com>
280 lines
8.5 KiB
C
280 lines
8.5 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "mdp5_kms.h"
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#include "drm_crtc.h"
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#include "drm_crtc_helper.h"
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struct mdp5_encoder {
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struct drm_encoder base;
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int intf;
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enum mdp5_intf intf_id;
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spinlock_t intf_lock; /* protect REG_MDP5_INTF_* registers */
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bool enabled;
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uint32_t bsc;
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};
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#define to_mdp5_encoder(x) container_of(x, struct mdp5_encoder, base)
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static struct mdp5_kms *get_kms(struct drm_encoder *encoder)
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{
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struct msm_drm_private *priv = encoder->dev->dev_private;
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return to_mdp5_kms(to_mdp_kms(priv->kms));
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}
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#ifdef CONFIG_MSM_BUS_SCALING
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#include <mach/board.h>
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#include <mach/msm_bus.h>
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#include <mach/msm_bus_board.h>
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#define MDP_BUS_VECTOR_ENTRY(ab_val, ib_val) \
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{ \
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.src = MSM_BUS_MASTER_MDP_PORT0, \
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.dst = MSM_BUS_SLAVE_EBI_CH0, \
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.ab = (ab_val), \
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.ib = (ib_val), \
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}
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static struct msm_bus_vectors mdp_bus_vectors[] = {
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MDP_BUS_VECTOR_ENTRY(0, 0),
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MDP_BUS_VECTOR_ENTRY(2000000000, 2000000000),
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};
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static struct msm_bus_paths mdp_bus_usecases[] = { {
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.num_paths = 1,
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.vectors = &mdp_bus_vectors[0],
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}, {
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.num_paths = 1,
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.vectors = &mdp_bus_vectors[1],
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} };
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static struct msm_bus_scale_pdata mdp_bus_scale_table = {
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.usecase = mdp_bus_usecases,
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.num_usecases = ARRAY_SIZE(mdp_bus_usecases),
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.name = "mdss_mdp",
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};
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static void bs_init(struct mdp5_encoder *mdp5_encoder)
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{
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mdp5_encoder->bsc = msm_bus_scale_register_client(
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&mdp_bus_scale_table);
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DBG("bus scale client: %08x", mdp5_encoder->bsc);
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}
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static void bs_fini(struct mdp5_encoder *mdp5_encoder)
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{
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if (mdp5_encoder->bsc) {
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msm_bus_scale_unregister_client(mdp5_encoder->bsc);
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mdp5_encoder->bsc = 0;
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}
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}
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static void bs_set(struct mdp5_encoder *mdp5_encoder, int idx)
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{
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if (mdp5_encoder->bsc) {
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DBG("set bus scaling: %d", idx);
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/* HACK: scaling down, and then immediately back up
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* seems to leave things broken (underflow).. so
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* never disable:
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*/
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idx = 1;
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msm_bus_scale_client_update_request(mdp5_encoder->bsc, idx);
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}
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}
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#else
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static void bs_init(struct mdp5_encoder *mdp5_encoder) {}
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static void bs_fini(struct mdp5_encoder *mdp5_encoder) {}
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static void bs_set(struct mdp5_encoder *mdp5_encoder, int idx) {}
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#endif
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static void mdp5_encoder_destroy(struct drm_encoder *encoder)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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bs_fini(mdp5_encoder);
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drm_encoder_cleanup(encoder);
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kfree(mdp5_encoder);
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}
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static const struct drm_encoder_funcs mdp5_encoder_funcs = {
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.destroy = mdp5_encoder_destroy,
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};
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static bool mdp5_encoder_mode_fixup(struct drm_encoder *encoder,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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return true;
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}
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static void mdp5_encoder_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_kms *mdp5_kms = get_kms(encoder);
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int intf = mdp5_encoder->intf;
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uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol;
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uint32_t display_v_start, display_v_end;
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uint32_t hsync_start_x, hsync_end_x;
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uint32_t format;
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unsigned long flags;
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mode = adjusted_mode;
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DBG("set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
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mode->base.id, mode->name,
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mode->vrefresh, mode->clock,
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mode->hdisplay, mode->hsync_start,
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mode->hsync_end, mode->htotal,
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mode->vdisplay, mode->vsync_start,
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mode->vsync_end, mode->vtotal,
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mode->type, mode->flags);
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ctrl_pol = 0;
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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ctrl_pol |= MDP5_INTF_POLARITY_CTL_HSYNC_LOW;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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ctrl_pol |= MDP5_INTF_POLARITY_CTL_VSYNC_LOW;
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/* probably need to get DATA_EN polarity from panel.. */
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dtv_hsync_skew = 0; /* get this from panel? */
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format = 0x213f; /* get this from panel? */
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hsync_start_x = (mode->htotal - mode->hsync_start);
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hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1;
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vsync_period = mode->vtotal * mode->htotal;
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vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal;
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display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew;
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display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1;
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spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_CTL(intf),
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MDP5_INTF_HSYNC_CTL_PULSEW(mode->hsync_end - mode->hsync_start) |
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MDP5_INTF_HSYNC_CTL_PERIOD(mode->htotal));
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mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_PERIOD_F0(intf), vsync_period);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_LEN_F0(intf), vsync_len);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_HCTL(intf),
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MDP5_INTF_DISPLAY_HCTL_START(hsync_start_x) |
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MDP5_INTF_DISPLAY_HCTL_END(hsync_end_x));
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mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VSTART_F0(intf), display_v_start);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VEND_F0(intf), display_v_end);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_BORDER_COLOR(intf), 0);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_UNDERFLOW_COLOR(intf), 0xff);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_SKEW(intf), dtv_hsync_skew);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_POLARITY_CTL(intf), ctrl_pol);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_HCTL(intf),
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MDP5_INTF_ACTIVE_HCTL_START(0) |
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MDP5_INTF_ACTIVE_HCTL_END(0));
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mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VSTART_F0(intf), 0);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VEND_F0(intf), 0);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_PANEL_FORMAT(intf), format);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(intf), 0x3); /* frame+line? */
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spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
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}
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static void mdp5_encoder_disable(struct drm_encoder *encoder)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_kms *mdp5_kms = get_kms(encoder);
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int intf = mdp5_encoder->intf;
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unsigned long flags;
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if (WARN_ON(!mdp5_encoder->enabled))
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return;
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spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intf), 0);
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spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
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/*
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* Wait for a vsync so we know the ENABLE=0 latched before
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* the (connector) source of the vsync's gets disabled,
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* otherwise we end up in a funny state if we re-enable
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* before the disable latches, which results that some of
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* the settings changes for the new modeset (like new
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* scanout buffer) don't latch properly..
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*/
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mdp_irq_wait(&mdp5_kms->base, intf2vblank(intf));
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bs_set(mdp5_encoder, 0);
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mdp5_encoder->enabled = false;
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}
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static void mdp5_encoder_enable(struct drm_encoder *encoder)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_kms *mdp5_kms = get_kms(encoder);
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int intf = mdp5_encoder->intf;
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unsigned long flags;
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if (WARN_ON(mdp5_encoder->enabled))
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return;
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mdp5_crtc_set_intf(encoder->crtc, mdp5_encoder->intf,
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mdp5_encoder->intf_id);
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bs_set(mdp5_encoder, 1);
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spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intf), 1);
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spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
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mdp5_encoder->enabled = false;
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}
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static const struct drm_encoder_helper_funcs mdp5_encoder_helper_funcs = {
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.mode_fixup = mdp5_encoder_mode_fixup,
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.mode_set = mdp5_encoder_mode_set,
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.prepare = mdp5_encoder_disable,
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.commit = mdp5_encoder_enable,
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};
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/* initialize encoder */
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struct drm_encoder *mdp5_encoder_init(struct drm_device *dev, int intf,
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enum mdp5_intf intf_id)
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{
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struct drm_encoder *encoder = NULL;
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struct mdp5_encoder *mdp5_encoder;
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int ret;
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mdp5_encoder = kzalloc(sizeof(*mdp5_encoder), GFP_KERNEL);
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if (!mdp5_encoder) {
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ret = -ENOMEM;
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goto fail;
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}
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mdp5_encoder->intf = intf;
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mdp5_encoder->intf_id = intf_id;
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encoder = &mdp5_encoder->base;
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spin_lock_init(&mdp5_encoder->intf_lock);
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drm_encoder_init(dev, encoder, &mdp5_encoder_funcs,
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DRM_MODE_ENCODER_TMDS);
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drm_encoder_helper_add(encoder, &mdp5_encoder_helper_funcs);
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bs_init(mdp5_encoder);
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return encoder;
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fail:
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if (encoder)
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mdp5_encoder_destroy(encoder);
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return ERR_PTR(ret);
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}
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