forked from Minki/linux
4671ea2041
The I915_READ/WRITE is not only a mmio read/write, it also contains
debug checking and Forcewake domain lookup. This is too heavy for
GVT ring switch case which access batch of mmio registers on ring
switch. We can handle Forcewake manually and use the raw
i915_read/write instead. The benefit from this is 2x faster mmio
switch performance.
Before After
cycles ~550000 ~250000
v2: Use existing I915_READ_FW/I915_WRITE_FW macro. (zhenyu)
Signed-off-by: Changbin Du <changbin.du@intel.com>
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
406 lines
11 KiB
C
406 lines
11 KiB
C
/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Eddie Dong <eddie.dong@intel.com>
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* Kevin Tian <kevin.tian@intel.com>
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*
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* Contributors:
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* Zhi Wang <zhi.a.wang@intel.com>
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* Changbin Du <changbin.du@intel.com>
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* Zhenyu Wang <zhenyuw@linux.intel.com>
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* Tina Zhang <tina.zhang@intel.com>
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* Bing Niu <bing.niu@intel.com>
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*
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*/
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#include "i915_drv.h"
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#include "gvt.h"
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#include "trace.h"
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struct render_mmio {
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int ring_id;
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i915_reg_t reg;
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u32 mask;
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bool in_context;
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u32 value;
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};
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static struct render_mmio gen8_render_mmio_list[] __cacheline_aligned = {
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{RCS, _MMIO(0x229c), 0xffff, false},
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{RCS, _MMIO(0x2248), 0x0, false},
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{RCS, _MMIO(0x2098), 0x0, false},
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{RCS, _MMIO(0x20c0), 0xffff, true},
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{RCS, _MMIO(0x24d0), 0, false},
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{RCS, _MMIO(0x24d4), 0, false},
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{RCS, _MMIO(0x24d8), 0, false},
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{RCS, _MMIO(0x24dc), 0, false},
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{RCS, _MMIO(0x24e0), 0, false},
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{RCS, _MMIO(0x24e4), 0, false},
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{RCS, _MMIO(0x24e8), 0, false},
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{RCS, _MMIO(0x24ec), 0, false},
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{RCS, _MMIO(0x24f0), 0, false},
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{RCS, _MMIO(0x24f4), 0, false},
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{RCS, _MMIO(0x24f8), 0, false},
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{RCS, _MMIO(0x24fc), 0, false},
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{RCS, _MMIO(0x7004), 0xffff, true},
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{RCS, _MMIO(0x7008), 0xffff, true},
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{RCS, _MMIO(0x7000), 0xffff, true},
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{RCS, _MMIO(0x7010), 0xffff, true},
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{RCS, _MMIO(0x7300), 0xffff, true},
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{RCS, _MMIO(0x83a4), 0xffff, true},
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{BCS, _MMIO(0x2229c), 0xffff, false},
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{BCS, _MMIO(0x2209c), 0xffff, false},
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{BCS, _MMIO(0x220c0), 0xffff, false},
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{BCS, _MMIO(0x22098), 0x0, false},
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{BCS, _MMIO(0x22028), 0x0, false},
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};
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static struct render_mmio gen9_render_mmio_list[] __cacheline_aligned = {
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{RCS, _MMIO(0x229c), 0xffff, false},
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{RCS, _MMIO(0x2248), 0x0, false},
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{RCS, _MMIO(0x2098), 0x0, false},
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{RCS, _MMIO(0x20c0), 0xffff, true},
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{RCS, _MMIO(0x24d0), 0, false},
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{RCS, _MMIO(0x24d4), 0, false},
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{RCS, _MMIO(0x24d8), 0, false},
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{RCS, _MMIO(0x24dc), 0, false},
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{RCS, _MMIO(0x24e0), 0, false},
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{RCS, _MMIO(0x24e4), 0, false},
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{RCS, _MMIO(0x24e8), 0, false},
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{RCS, _MMIO(0x24ec), 0, false},
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{RCS, _MMIO(0x24f0), 0, false},
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{RCS, _MMIO(0x24f4), 0, false},
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{RCS, _MMIO(0x24f8), 0, false},
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{RCS, _MMIO(0x24fc), 0, false},
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{RCS, _MMIO(0x7004), 0xffff, true},
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{RCS, _MMIO(0x7008), 0xffff, true},
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{RCS, _MMIO(0x7000), 0xffff, true},
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{RCS, _MMIO(0x7010), 0xffff, true},
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{RCS, _MMIO(0x7300), 0xffff, true},
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{RCS, _MMIO(0x83a4), 0xffff, true},
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{RCS, _MMIO(0x40e0), 0, false},
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{RCS, _MMIO(0x40e4), 0, false},
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{RCS, _MMIO(0x2580), 0xffff, true},
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{RCS, _MMIO(0x7014), 0xffff, true},
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{RCS, _MMIO(0x20ec), 0xffff, false},
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{RCS, _MMIO(0xb118), 0, false},
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{RCS, _MMIO(0xe100), 0xffff, true},
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{RCS, _MMIO(0xe180), 0xffff, true},
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{RCS, _MMIO(0xe184), 0xffff, true},
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{RCS, _MMIO(0xe188), 0xffff, true},
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{RCS, _MMIO(0xe194), 0xffff, true},
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{RCS, _MMIO(0x4de0), 0, false},
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{RCS, _MMIO(0x4de4), 0, false},
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{RCS, _MMIO(0x4de8), 0, false},
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{RCS, _MMIO(0x4dec), 0, false},
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{RCS, _MMIO(0x4df0), 0, false},
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{RCS, _MMIO(0x4df4), 0, false},
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{BCS, _MMIO(0x2229c), 0xffff, false},
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{BCS, _MMIO(0x2209c), 0xffff, false},
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{BCS, _MMIO(0x220c0), 0xffff, false},
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{BCS, _MMIO(0x22098), 0x0, false},
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{BCS, _MMIO(0x22028), 0x0, false},
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{VCS2, _MMIO(0x1c028), 0xffff, false},
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{VECS, _MMIO(0x1a028), 0xffff, false},
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{RCS, _MMIO(0x7304), 0xffff, true},
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{RCS, _MMIO(0x2248), 0x0, false},
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{RCS, _MMIO(0x940c), 0x0, false},
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{RCS, _MMIO(0x4ab8), 0x0, false},
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{RCS, _MMIO(0x4ab0), 0x0, false},
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{RCS, _MMIO(0x20d4), 0x0, false},
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{RCS, _MMIO(0xb004), 0x0, false},
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{RCS, _MMIO(0x20a0), 0x0, false},
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{RCS, _MMIO(0x20e4), 0xffff, false},
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};
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static u32 gen9_render_mocs[I915_NUM_ENGINES][64];
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static u32 gen9_render_mocs_L3[32];
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static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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enum forcewake_domains fw;
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i915_reg_t reg;
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u32 regs[] = {
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[RCS] = 0x4260,
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[VCS] = 0x4264,
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[VCS2] = 0x4268,
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[BCS] = 0x426c,
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[VECS] = 0x4270,
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};
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if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
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return;
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if (!test_and_clear_bit(ring_id, (void *)vgpu->tlb_handle_pending))
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return;
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reg = _MMIO(regs[ring_id]);
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/* WaForceWakeRenderDuringMmioTLBInvalidate:skl
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* we need to put a forcewake when invalidating RCS TLB caches,
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* otherwise device can go to RC6 state and interrupt invalidation
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* process
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*/
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fw = intel_uncore_forcewake_for_reg(dev_priv, reg,
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FW_REG_READ | FW_REG_WRITE);
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if (ring_id == RCS && (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
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fw |= FORCEWAKE_RENDER;
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intel_uncore_forcewake_get(dev_priv, fw);
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I915_WRITE_FW(reg, 0x1);
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if (wait_for_atomic((I915_READ_FW(reg) == 0), 50))
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gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id);
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else
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vgpu_vreg(vgpu, regs[ring_id]) = 0;
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intel_uncore_forcewake_put(dev_priv, fw);
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gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
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}
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static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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i915_reg_t offset, l3_offset;
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u32 regs[] = {
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[RCS] = 0xc800,
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[VCS] = 0xc900,
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[VCS2] = 0xca00,
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[BCS] = 0xcc00,
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[VECS] = 0xcb00,
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};
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int i;
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if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
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return;
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offset.reg = regs[ring_id];
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for (i = 0; i < 64; i++) {
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gen9_render_mocs[ring_id][i] = I915_READ_FW(offset);
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I915_WRITE(offset, vgpu_vreg(vgpu, offset));
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offset.reg += 4;
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}
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if (ring_id == RCS) {
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l3_offset.reg = 0xb020;
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for (i = 0; i < 32; i++) {
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gen9_render_mocs_L3[i] = I915_READ_FW(l3_offset);
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I915_WRITE_FW(l3_offset, vgpu_vreg(vgpu, l3_offset));
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l3_offset.reg += 4;
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}
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}
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}
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static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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i915_reg_t offset, l3_offset;
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u32 regs[] = {
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[RCS] = 0xc800,
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[VCS] = 0xc900,
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[VCS2] = 0xca00,
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[BCS] = 0xcc00,
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[VECS] = 0xcb00,
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};
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int i;
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if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
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return;
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offset.reg = regs[ring_id];
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for (i = 0; i < 64; i++) {
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vgpu_vreg(vgpu, offset) = I915_READ_FW(offset);
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I915_WRITE_FW(offset, gen9_render_mocs[ring_id][i]);
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offset.reg += 4;
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}
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if (ring_id == RCS) {
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l3_offset.reg = 0xb020;
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for (i = 0; i < 32; i++) {
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vgpu_vreg(vgpu, l3_offset) = I915_READ_FW(l3_offset);
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I915_WRITE_FW(l3_offset, gen9_render_mocs_L3[i]);
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l3_offset.reg += 4;
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}
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}
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}
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#define CTX_CONTEXT_CONTROL_VAL 0x03
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/* Switch ring mmio values (context) from host to a vgpu. */
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static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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struct render_mmio *mmio;
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u32 v;
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int i, array_size;
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u32 *reg_state = vgpu->shadow_ctx->engine[ring_id].lrc_reg_state;
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u32 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL];
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u32 inhibit_mask =
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_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
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i915_reg_t last_reg = _MMIO(0);
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if (IS_SKYLAKE(vgpu->gvt->dev_priv)
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|| IS_KABYLAKE(vgpu->gvt->dev_priv)) {
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mmio = gen9_render_mmio_list;
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array_size = ARRAY_SIZE(gen9_render_mmio_list);
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load_mocs(vgpu, ring_id);
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} else {
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mmio = gen8_render_mmio_list;
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array_size = ARRAY_SIZE(gen8_render_mmio_list);
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}
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for (i = 0; i < array_size; i++, mmio++) {
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if (mmio->ring_id != ring_id)
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continue;
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mmio->value = I915_READ_FW(mmio->reg);
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/*
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* if it is an inhibit context, load in_context mmio
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* into HW by mmio write. If it is not, skip this mmio
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* write.
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*/
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if (mmio->in_context &&
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((ctx_ctrl & inhibit_mask) != inhibit_mask) &&
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i915.enable_execlists)
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continue;
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if (mmio->mask)
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v = vgpu_vreg(vgpu, mmio->reg) | (mmio->mask << 16);
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else
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v = vgpu_vreg(vgpu, mmio->reg);
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I915_WRITE_FW(mmio->reg, v);
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last_reg = mmio->reg;
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trace_render_mmio(vgpu->id, "load",
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i915_mmio_reg_offset(mmio->reg),
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mmio->value, v);
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}
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/* Make sure the swiched MMIOs has taken effect. */
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if (likely(INTEL_GVT_MMIO_OFFSET(last_reg)))
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I915_READ_FW(last_reg);
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handle_tlb_pending_event(vgpu, ring_id);
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}
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/* Switch ring mmio values (context) from vgpu to host. */
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static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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struct render_mmio *mmio;
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i915_reg_t last_reg = _MMIO(0);
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u32 v;
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int i, array_size;
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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mmio = gen9_render_mmio_list;
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array_size = ARRAY_SIZE(gen9_render_mmio_list);
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restore_mocs(vgpu, ring_id);
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} else {
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mmio = gen8_render_mmio_list;
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array_size = ARRAY_SIZE(gen8_render_mmio_list);
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}
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for (i = 0; i < array_size; i++, mmio++) {
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if (mmio->ring_id != ring_id)
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continue;
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vgpu_vreg(vgpu, mmio->reg) = I915_READ_FW(mmio->reg);
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if (mmio->mask) {
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vgpu_vreg(vgpu, mmio->reg) &= ~(mmio->mask << 16);
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v = mmio->value | (mmio->mask << 16);
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} else
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v = mmio->value;
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if (mmio->in_context)
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continue;
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I915_WRITE_FW(mmio->reg, v);
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last_reg = mmio->reg;
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trace_render_mmio(vgpu->id, "restore",
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i915_mmio_reg_offset(mmio->reg),
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mmio->value, v);
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}
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/* Make sure the swiched MMIOs has taken effect. */
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if (likely(INTEL_GVT_MMIO_OFFSET(last_reg)))
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I915_READ_FW(last_reg);
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}
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/**
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* intel_gvt_switch_render_mmio - switch mmio context of specific engine
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* @pre: the last vGPU that own the engine
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* @next: the vGPU to switch to
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* @ring_id: specify the engine
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*
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* If pre is null indicates that host own the engine. If next is null
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* indicates that we are switching to host workload.
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*/
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void intel_gvt_switch_mmio(struct intel_vgpu *pre,
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struct intel_vgpu *next, int ring_id)
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{
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struct drm_i915_private *dev_priv;
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if (WARN_ON(!pre && !next))
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return;
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gvt_dbg_render("switch ring %d from %s to %s\n", ring_id,
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pre ? "vGPU" : "host", next ? "vGPU" : "HOST");
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dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
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/**
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* We are using raw mmio access wrapper to improve the
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* performace for batch mmio read/write, so we need
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* handle forcewake mannually.
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*/
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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/**
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* TODO: Optimize for vGPU to vGPU switch by merging
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* switch_mmio_to_host() and switch_mmio_to_vgpu().
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*/
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if (pre)
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switch_mmio_to_host(pre, ring_id);
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if (next)
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switch_mmio_to_vgpu(next, ring_id);
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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}
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