ae0d7cbc99
This patch causes the kernel to mux the SERIRQ interrupt to the SERIRQ pin of the PIIX4 and to enable that interrupt. The kernel depends upon the interrupt when using the SuperIO UARTs (ttyS0 & ttyS1) but previously would not configure it, instead relying upon the bootloader having done so. If that is not the case then the typical result is that the system appears to hang once it reaches userland as no output is displayed on the UART. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6182/
54 lines
2.1 KiB
C
54 lines
2.1 KiB
C
/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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* Copyright (C) 2013 Imagination Technologies Ltd.
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Register definitions for Intel PIIX4 South Bridge Device.
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*/
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#ifndef __ASM_MIPS_BOARDS_PIIX4_H
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#define __ASM_MIPS_BOARDS_PIIX4_H
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/* PIRQX Route Control */
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#define PIIX4_FUNC0_PIRQRC 0x60
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#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7)
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#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf
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#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16
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/* SERIRQ Control */
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#define PIIX4_FUNC0_SERIRQC 0x64
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#define PIIX4_FUNC0_SERIRQC_EN (1 << 7)
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#define PIIX4_FUNC0_SERIRQC_CONT (1 << 6)
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/* Top Of Memory */
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#define PIIX4_FUNC0_TOM 0x69
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#define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0
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/* Deterministic Latency Control */
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#define PIIX4_FUNC0_DLC 0x82
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#define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2)
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#define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1)
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#define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0)
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/* General Configuration */
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#define PIIX4_FUNC0_GENCFG 0xb0
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#define PIIX4_FUNC0_GENCFG_SERIRQ (1 << 16)
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/* IDE Timing */
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#define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40
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#define PIIX4_FUNC1_IDETIM_PRIMARY_HI 0x41
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#define PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN (1 << 7)
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#define PIIX4_FUNC1_IDETIM_SECONDARY_LO 0x42
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#define PIIX4_FUNC1_IDETIM_SECONDARY_HI 0x43
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#define PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN (1 << 7)
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#endif /* __ASM_MIPS_BOARDS_PIIX4_H */
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