When the SDI output was converted to DRM bridge, the atomic versions of
enable and disable funcs were used. This was not intended, as that would
require implementing other atomic funcs too. This leads to:
WARNING: CPU: 0 PID: 18 at drivers/gpu/drm/drm_bridge.c:708 drm_atomic_helper_commit_modeset_enables+0x134/0x268
and display not working.
Fix this by using the legacy enable/disable funcs.
Fixes: 8bef8a6d5d
("drm/omap: sdi: Register a drm_bridge")
Reported-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Tested-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: stable@vger.kernel.org # v5.7+
Link: https://patchwork.freedesktop.org/patch/msgid/20201127085241.848461-1-tomi.valkeinen@ti.com
399 lines
8.8 KiB
C
399 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2009 Nokia Corporation
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* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
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*/
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#define DSS_SUBSYS_NAME "SDI"
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/string.h>
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#include <drm/drm_bridge.h>
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#include "dss.h"
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#include "omapdss.h"
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struct sdi_device {
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struct platform_device *pdev;
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struct dss_device *dss;
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bool update_enabled;
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struct regulator *vdds_sdi_reg;
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struct dss_lcd_mgr_config mgr_config;
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unsigned long pixelclock;
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int datapairs;
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struct omap_dss_device output;
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struct drm_bridge bridge;
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};
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#define drm_bridge_to_sdi(bridge) \
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container_of(bridge, struct sdi_device, bridge)
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struct sdi_clk_calc_ctx {
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struct sdi_device *sdi;
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unsigned long pck_min, pck_max;
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unsigned long fck;
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struct dispc_clock_info dispc_cinfo;
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};
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static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
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unsigned long pck, void *data)
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{
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struct sdi_clk_calc_ctx *ctx = data;
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ctx->dispc_cinfo.lck_div = lckd;
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ctx->dispc_cinfo.pck_div = pckd;
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ctx->dispc_cinfo.lck = lck;
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ctx->dispc_cinfo.pck = pck;
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return true;
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}
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static bool dpi_calc_dss_cb(unsigned long fck, void *data)
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{
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struct sdi_clk_calc_ctx *ctx = data;
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ctx->fck = fck;
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return dispc_div_calc(ctx->sdi->dss->dispc, fck,
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ctx->pck_min, ctx->pck_max,
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dpi_calc_dispc_cb, ctx);
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}
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static int sdi_calc_clock_div(struct sdi_device *sdi, unsigned long pclk,
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unsigned long *fck,
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struct dispc_clock_info *dispc_cinfo)
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{
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int i;
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struct sdi_clk_calc_ctx ctx;
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/*
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* DSS fclk gives us very few possibilities, so finding a good pixel
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* clock may not be possible. We try multiple times to find the clock,
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* each time widening the pixel clock range we look for, up to
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* +/- 1MHz.
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*/
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for (i = 0; i < 10; ++i) {
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bool ok;
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memset(&ctx, 0, sizeof(ctx));
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ctx.sdi = sdi;
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if (pclk > 1000 * i * i * i)
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ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu);
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else
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ctx.pck_min = 0;
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ctx.pck_max = pclk + 1000 * i * i * i;
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ok = dss_div_calc(sdi->dss, pclk, ctx.pck_min,
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dpi_calc_dss_cb, &ctx);
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if (ok) {
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*fck = ctx.fck;
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*dispc_cinfo = ctx.dispc_cinfo;
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return 0;
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}
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}
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return -EINVAL;
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}
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static void sdi_config_lcd_manager(struct sdi_device *sdi)
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{
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sdi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
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sdi->mgr_config.stallmode = false;
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sdi->mgr_config.fifohandcheck = false;
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sdi->mgr_config.video_port_width = 24;
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sdi->mgr_config.lcden_sig_polarity = 1;
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dss_mgr_set_lcd_config(&sdi->output, &sdi->mgr_config);
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}
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/* -----------------------------------------------------------------------------
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* DRM Bridge Operations
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*/
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static int sdi_bridge_attach(struct drm_bridge *bridge,
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enum drm_bridge_attach_flags flags)
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{
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struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
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if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
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return -EINVAL;
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return drm_bridge_attach(bridge->encoder, sdi->output.next_bridge,
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bridge, flags);
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}
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static enum drm_mode_status
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sdi_bridge_mode_valid(struct drm_bridge *bridge,
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const struct drm_display_info *info,
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const struct drm_display_mode *mode)
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{
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struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
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unsigned long pixelclock = mode->clock * 1000;
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struct dispc_clock_info dispc_cinfo;
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unsigned long fck;
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int ret;
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if (pixelclock == 0)
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return MODE_NOCLOCK;
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ret = sdi_calc_clock_div(sdi, pixelclock, &fck, &dispc_cinfo);
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if (ret < 0)
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return MODE_CLOCK_RANGE;
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return MODE_OK;
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}
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static bool sdi_bridge_mode_fixup(struct drm_bridge *bridge,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
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unsigned long pixelclock = mode->clock * 1000;
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struct dispc_clock_info dispc_cinfo;
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unsigned long fck;
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unsigned long pck;
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int ret;
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ret = sdi_calc_clock_div(sdi, pixelclock, &fck, &dispc_cinfo);
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if (ret < 0)
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return false;
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pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div;
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if (pck != pixelclock)
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dev_dbg(&sdi->pdev->dev,
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"pixel clock adjusted from %lu Hz to %lu Hz\n",
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pixelclock, pck);
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adjusted_mode->clock = pck / 1000;
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return true;
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}
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static void sdi_bridge_mode_set(struct drm_bridge *bridge,
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const struct drm_display_mode *mode,
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const struct drm_display_mode *adjusted_mode)
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{
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struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
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sdi->pixelclock = adjusted_mode->clock * 1000;
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}
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static void sdi_bridge_enable(struct drm_bridge *bridge)
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{
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struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
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struct dispc_clock_info dispc_cinfo;
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unsigned long fck;
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int r;
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r = regulator_enable(sdi->vdds_sdi_reg);
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if (r)
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return;
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r = dispc_runtime_get(sdi->dss->dispc);
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if (r)
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goto err_get_dispc;
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r = sdi_calc_clock_div(sdi, sdi->pixelclock, &fck, &dispc_cinfo);
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if (r)
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goto err_calc_clock_div;
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sdi->mgr_config.clock_info = dispc_cinfo;
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r = dss_set_fck_rate(sdi->dss, fck);
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if (r)
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goto err_set_dss_clock_div;
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sdi_config_lcd_manager(sdi);
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/*
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* LCLK and PCLK divisors are located in shadow registers, and we
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* normally write them to DISPC registers when enabling the output.
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* However, SDI uses pck-free as source clock for its PLL, and pck-free
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* is affected by the divisors. And as we need the PLL before enabling
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* the output, we need to write the divisors early.
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*
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* It seems just writing to the DISPC register is enough, and we don't
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* need to care about the shadow register mechanism for pck-free. The
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* exact reason for this is unknown.
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*/
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dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel,
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&sdi->mgr_config.clock_info);
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dss_sdi_init(sdi->dss, sdi->datapairs);
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r = dss_sdi_enable(sdi->dss);
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if (r)
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goto err_sdi_enable;
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mdelay(2);
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r = dss_mgr_enable(&sdi->output);
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if (r)
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goto err_mgr_enable;
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return;
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err_mgr_enable:
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dss_sdi_disable(sdi->dss);
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err_sdi_enable:
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err_set_dss_clock_div:
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err_calc_clock_div:
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dispc_runtime_put(sdi->dss->dispc);
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err_get_dispc:
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regulator_disable(sdi->vdds_sdi_reg);
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}
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static void sdi_bridge_disable(struct drm_bridge *bridge)
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{
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struct sdi_device *sdi = drm_bridge_to_sdi(bridge);
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dss_mgr_disable(&sdi->output);
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dss_sdi_disable(sdi->dss);
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dispc_runtime_put(sdi->dss->dispc);
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regulator_disable(sdi->vdds_sdi_reg);
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}
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static const struct drm_bridge_funcs sdi_bridge_funcs = {
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.attach = sdi_bridge_attach,
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.mode_valid = sdi_bridge_mode_valid,
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.mode_fixup = sdi_bridge_mode_fixup,
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.mode_set = sdi_bridge_mode_set,
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.enable = sdi_bridge_enable,
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.disable = sdi_bridge_disable,
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};
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static void sdi_bridge_init(struct sdi_device *sdi)
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{
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sdi->bridge.funcs = &sdi_bridge_funcs;
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sdi->bridge.of_node = sdi->pdev->dev.of_node;
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sdi->bridge.type = DRM_MODE_CONNECTOR_LVDS;
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drm_bridge_add(&sdi->bridge);
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}
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static void sdi_bridge_cleanup(struct sdi_device *sdi)
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{
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drm_bridge_remove(&sdi->bridge);
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}
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/* -----------------------------------------------------------------------------
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* Initialisation and Cleanup
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*/
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static int sdi_init_output(struct sdi_device *sdi)
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{
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struct omap_dss_device *out = &sdi->output;
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int r;
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sdi_bridge_init(sdi);
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out->dev = &sdi->pdev->dev;
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out->id = OMAP_DSS_OUTPUT_SDI;
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out->type = OMAP_DISPLAY_TYPE_SDI;
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out->name = "sdi.0";
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out->dispc_channel = OMAP_DSS_CHANNEL_LCD;
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/* We have SDI only on OMAP3, where it's on port 1 */
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out->of_port = 1;
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out->owner = THIS_MODULE;
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out->bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE /* 15.5.9.1.2 */
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| DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE;
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r = omapdss_device_init_output(out, &sdi->bridge);
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if (r < 0) {
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sdi_bridge_cleanup(sdi);
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return r;
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}
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omapdss_device_register(out);
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return 0;
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}
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static void sdi_uninit_output(struct sdi_device *sdi)
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{
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omapdss_device_unregister(&sdi->output);
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omapdss_device_cleanup_output(&sdi->output);
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sdi_bridge_cleanup(sdi);
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}
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int sdi_init_port(struct dss_device *dss, struct platform_device *pdev,
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struct device_node *port)
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{
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struct sdi_device *sdi;
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struct device_node *ep;
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u32 datapairs;
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int r;
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sdi = kzalloc(sizeof(*sdi), GFP_KERNEL);
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if (!sdi)
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return -ENOMEM;
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ep = of_get_next_child(port, NULL);
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if (!ep) {
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r = 0;
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goto err_free;
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}
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r = of_property_read_u32(ep, "datapairs", &datapairs);
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of_node_put(ep);
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if (r) {
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DSSERR("failed to parse datapairs\n");
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goto err_free;
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}
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sdi->datapairs = datapairs;
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sdi->dss = dss;
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sdi->pdev = pdev;
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port->data = sdi;
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sdi->vdds_sdi_reg = devm_regulator_get(&pdev->dev, "vdds_sdi");
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if (IS_ERR(sdi->vdds_sdi_reg)) {
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r = PTR_ERR(sdi->vdds_sdi_reg);
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if (r != -EPROBE_DEFER)
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DSSERR("can't get VDDS_SDI regulator\n");
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goto err_free;
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}
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r = sdi_init_output(sdi);
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if (r)
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goto err_free;
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return 0;
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err_free:
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kfree(sdi);
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return r;
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}
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void sdi_uninit_port(struct device_node *port)
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{
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struct sdi_device *sdi = port->data;
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if (!sdi)
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return;
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sdi_uninit_output(sdi);
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kfree(sdi);
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}
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