forked from Minki/linux
aa5b537b0e
* Support for Sv57-based virtual memory. * Various improvements for the MicroChip PolarFire SOC and the associated Icicle dev board, which should allow upstream kernels to boot without any additional modifications. * An improved memmove() implementation. * Support for the new Ssconfpmf and SBI PMU extensions, which allows for a much more useful perf implementation on RISC-V systems. * Support for restartable sequences. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmI96FcTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiQBFD/425+6xmoOru6Wiki3Ja0fqQToNrQyW IbmE/8AxUP7UxMvJSNzvQm8deXgklzvmegXCtnjwZZins971vMzzDSI83k/zn8I7 m5thVC9z01BjodV+pvIp/44hS6FesolOLzkVHksX0Zh6h0iidrc34Qf5HrqvvNfN CZ/4K1+E9ig5r9qZp4WdvocCXj+FzwF/30GjKoW9vwA599CEG/dCo+TNN9GKD6XS k+xiUGwlIRA+kCLSPFCi7ev9XPr1tCmQB7uB8Igcvr7Y3mWl8HKfajQVXBnXNRC3 ifbDxpx1elJiLPyf7Rza8jIDwDhLQdxBiwPgDgP9h9R4x0uF4efq8PzLzFlFmaE+ 9Z9thfykBb5dXYDFDje9bAOXvKnGk7Iqxdsz0qWo/ChEQawX1+11bJb0TNN8QTT9 YvlQfUXgb1dmEcj5yG2uVE1Y8L7YNLRMsZU3W3FbmPJZoavSOuU4x0yCGeLyv597 76af3nuBJ5v80Db97gu6St+HIACeevKflsZUf/8GS/p7d1DlvmrWzQUMEycxPTG9 UZpZak58jh7AqQ9JbLnavhwmeacY50vpZOw6QHGAHSN+8daCPlOHDG7Ver7Z+kNj +srJ7iKMvLnnaEjGNgavfxdqTOme1gv4LWs/JdHYMkpphqVN92xBDJnhXTPRVZiQ 0x39vK86qtB46A== =Omc6 -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for Sv57-based virtual memory. - Various improvements for the MicroChip PolarFire SOC and the associated Icicle dev board, which should allow upstream kernels to boot without any additional modifications. - An improved memmove() implementation. - Support for the new Ssconfpmf and SBI PMU extensions, which allows for a much more useful perf implementation on RISC-V systems. - Support for restartable sequences. * tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (36 commits) rseq/selftests: Add support for RISC-V RISC-V: Add support for restartable sequence MAINTAINERS: Add entry for RISC-V PMU drivers Documentation: riscv: Remove the old documentation RISC-V: Add sscofpmf extension support RISC-V: Add perf platform driver based on SBI PMU extension RISC-V: Add RISC-V SBI PMU extension definitions RISC-V: Add a simple platform driver for RISC-V legacy perf RISC-V: Add a perf core library for pmu drivers RISC-V: Add CSR encodings for all HPMCOUNTERS RISC-V: Remove the current perf implementation RISC-V: Improve /proc/cpuinfo output for ISA extensions RISC-V: Do no continue isa string parsing without correct XLEN RISC-V: Implement multi-letter ISA extension probing framework RISC-V: Extract multi-letter extension names from "riscv, isa" RISC-V: Minimal parser for "riscv, isa" strings RISC-V: Correctly print supported extensions riscv: Fixed misaligned memory access. Fixed pointer comparison. MAINTAINERS: update riscv/microchip entry riscv: dts: microchip: add new peripherals to icicle kit device tree ...
196 lines
5.9 KiB
Plaintext
196 lines
5.9 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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#
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# Performance Monitor Drivers
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#
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menu "Performance monitor support"
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depends on PERF_EVENTS
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config ARM_CCI_PMU
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tristate "ARM CCI PMU driver"
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depends on (ARM && CPU_V7) || ARM64
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select ARM_CCI
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help
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Support for PMU events monitoring on the ARM CCI (Cache Coherent
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Interconnect) family of products.
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If compiled as a module, it will be called arm-cci.
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config ARM_CCI400_PMU
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bool "support CCI-400"
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default y
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depends on ARM_CCI_PMU
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select ARM_CCI400_COMMON
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help
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CCI-400 provides 4 independent event counters counting events related
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to the connected slave/master interfaces, plus a cycle counter.
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config ARM_CCI5xx_PMU
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bool "support CCI-500/CCI-550"
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default y
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depends on ARM_CCI_PMU
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help
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CCI-500/CCI-550 both provide 8 independent event counters, which can
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count events pertaining to the slave/master interfaces as well as the
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internal events to the CCI.
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config ARM_CCN
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tristate "ARM CCN driver support"
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depends on ARM || ARM64 || COMPILE_TEST
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help
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PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
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interconnect.
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config ARM_CMN
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tristate "Arm CMN-600 PMU support"
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depends on ARM64 || COMPILE_TEST
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help
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Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
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Network interconnect.
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config ARM_PMU
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depends on ARM || ARM64
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bool "ARM PMU framework"
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default y
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help
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Say y if you want to use CPU performance monitors on ARM-based
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systems.
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config RISCV_PMU
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depends on RISCV
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bool "RISC-V PMU framework"
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default y
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help
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Say y if you want to use CPU performance monitors on RISCV-based
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systems. This provides the core PMU framework that abstracts common
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PMU functionalities in a core library so that different PMU drivers
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can reuse it.
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config RISCV_PMU_LEGACY
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depends on RISCV_PMU
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bool "RISC-V legacy PMU implementation"
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default y
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help
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Say y if you want to use the legacy CPU performance monitor
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implementation on RISC-V based systems. This only allows counting
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of cycle/instruction counter and doesn't support counter overflow,
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or programmable counters. It will be removed in future.
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config RISCV_PMU_SBI
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depends on RISCV_PMU && RISCV_SBI
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bool "RISC-V PMU based on SBI PMU extension"
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default y
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help
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Say y if you want to use the CPU performance monitor
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using SBI PMU extension on RISC-V based systems. This option provides
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full perf feature support i.e. counter overflow, privilege mode
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filtering, counter configuration.
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config ARM_PMU_ACPI
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depends on ARM_PMU && ACPI
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def_bool y
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config ARM_SMMU_V3_PMU
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tristate "ARM SMMUv3 Performance Monitors Extension"
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depends on (ARM64 && ACPI) || (COMPILE_TEST && 64BIT)
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depends on GENERIC_MSI_IRQ_DOMAIN
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help
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Provides support for the ARM SMMUv3 Performance Monitor Counter
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Groups (PMCG), which provide monitoring of transactions passing
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through the SMMU and allow the resulting information to be filtered
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based on the Stream ID of the corresponding master.
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config ARM_DSU_PMU
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tristate "ARM DynamIQ Shared Unit (DSU) PMU"
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depends on ARM64
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help
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Provides support for performance monitor unit in ARM DynamIQ Shared
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Unit (DSU). The DSU integrates one or more cores with an L3 memory
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system, control logic. The PMU allows counting various events related
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to DSU.
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config FSL_IMX8_DDR_PMU
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tristate "Freescale i.MX8 DDR perf monitor"
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depends on ARCH_MXC || COMPILE_TEST
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help
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Provides support for the DDR performance monitor in i.MX8, which
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can give information about memory throughput and other related
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events.
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config QCOM_L2_PMU
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bool "Qualcomm Technologies L2-cache PMU"
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depends on ARCH_QCOM && ARM64 && ACPI
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select QCOM_KRYO_L2_ACCESSORS
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help
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Provides support for the L2 cache performance monitor unit (PMU)
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in Qualcomm Technologies processors.
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Adds the L2 cache PMU into the perf events subsystem for
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monitoring L2 cache events.
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config QCOM_L3_PMU
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bool "Qualcomm Technologies L3-cache PMU"
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depends on ARCH_QCOM && ARM64 && ACPI
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select QCOM_IRQ_COMBINER
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help
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Provides support for the L3 cache performance monitor unit (PMU)
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in Qualcomm Technologies processors.
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Adds the L3 cache PMU into the perf events subsystem for
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monitoring L3 cache events.
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config THUNDERX2_PMU
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tristate "Cavium ThunderX2 SoC PMU UNCORE"
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depends on ARCH_THUNDER2 || COMPILE_TEST
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depends on NUMA && ACPI
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default m
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help
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Provides support for ThunderX2 UNCORE events.
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The SoC has PMU support in its L3 cache controller (L3C) and
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in the DDR4 Memory Controller (DMC).
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config XGENE_PMU
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depends on ARCH_XGENE || (COMPILE_TEST && 64BIT)
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bool "APM X-Gene SoC PMU"
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default n
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help
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Say y if you want to use APM X-Gene SoC performance monitors.
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config ARM_SPE_PMU
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tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
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depends on ARM64
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help
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Enable perf support for the ARMv8.2 Statistical Profiling
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Extension, which provides periodic sampling of operations in
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the CPU pipeline and reports this via the perf AUX interface.
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config ARM_DMC620_PMU
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tristate "Enable PMU support for the ARM DMC-620 memory controller"
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depends on (ARM64 && ACPI) || COMPILE_TEST
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help
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Support for PMU events monitoring on the ARM DMC-620 memory
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controller.
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config MARVELL_CN10K_TAD_PMU
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tristate "Marvell CN10K LLC-TAD PMU"
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depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT)
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help
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Provides support for Last-Level cache Tag-and-data Units (LLC-TAD)
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performance monitors on CN10K family silicons.
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config APPLE_M1_CPU_PMU
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bool "Apple M1 CPU PMU support"
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depends on ARM_PMU && ARCH_APPLE
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help
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Provides support for the non-architectural CPU PMUs present on
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the Apple M1 SoCs and derivatives.
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source "drivers/perf/hisilicon/Kconfig"
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config MARVELL_CN10K_DDR_PMU
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tristate "Enable MARVELL CN10K DRAM Subsystem(DSS) PMU Support"
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depends on ARM64 || (COMPILE_TEST && 64BIT)
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help
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Enable perf support for Marvell DDR Performance monitoring
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event on CN10K platform.
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endmenu
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