forked from Minki/linux
8c3583b634
instead of reading the registers everytime the current implementation respect the following constrain: - allow 1 to n soc to be enabled - allow to have a virtual cpu type and subtype - always detect the cpu type and subtype and report it - detect if the soc support is enabled - prepare for sysfs export support - drop soc specific code via compiler when the soc not enabled (via cpu_is_xxx) Today if we read the exid we will have the same value for 9g35 and 9m11 and we will need to check the cidr too with the new implementation we just need to check the soc subtype this will also allow to have specific virtual subtype for rm9200 which the board will have to specify via at91rm9200_set_type(int) as we have no way to detect it. this implementation is inspired by the SH cpu detection support Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
215 lines
6.2 KiB
C
215 lines
6.2 KiB
C
/*
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* arch/arm/mach-at91/include/mach/cpu.h
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*
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* Copyright (C) 2006 SAN People
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* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#ifndef __MACH_CPU_H__
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#define __MACH_CPU_H__
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#define ARCH_ID_AT91RM9200 0x09290780
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#define ARCH_ID_AT91SAM9260 0x019803a0
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#define ARCH_ID_AT91SAM9261 0x019703a0
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#define ARCH_ID_AT91SAM9263 0x019607a0
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#define ARCH_ID_AT91SAM9G10 0x019903a0
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#define ARCH_ID_AT91SAM9G20 0x019905a0
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#define ARCH_ID_AT91SAM9RL64 0x019b03a0
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#define ARCH_ID_AT91SAM9G45 0x819b05a0
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#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
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#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
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#define ARCH_ID_AT91SAM9X5 0x819a05a0
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#define ARCH_ID_AT91CAP9 0x039A03A0
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#define ARCH_ID_AT91SAM9XE128 0x329973a0
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#define ARCH_ID_AT91SAM9XE256 0x329a93a0
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#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
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#define ARCH_ID_AT91M40800 0x14080044
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#define ARCH_ID_AT91R40807 0x44080746
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#define ARCH_ID_AT91M40807 0x14080745
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#define ARCH_ID_AT91R40008 0x44000840
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#define ARCH_EXID_AT91SAM9M11 0x00000001
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#define ARCH_EXID_AT91SAM9M10 0x00000002
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#define ARCH_EXID_AT91SAM9G46 0x00000003
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#define ARCH_EXID_AT91SAM9G45 0x00000004
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#define ARCH_EXID_AT91SAM9G15 0x00000000
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#define ARCH_EXID_AT91SAM9G35 0x00000001
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#define ARCH_EXID_AT91SAM9X35 0x00000002
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#define ARCH_EXID_AT91SAM9G25 0x00000003
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#define ARCH_EXID_AT91SAM9X25 0x00000004
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#define ARCH_FAMILY_AT91X92 0x09200000
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#define ARCH_FAMILY_AT91SAM9 0x01900000
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#define ARCH_FAMILY_AT91SAM9XE 0x02900000
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/* PMC revision */
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#define ARCH_REVISION_CAP9_B 0x399
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#define ARCH_REVISION_CAP9_C 0x601
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/* RM9200 type */
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#define ARCH_REVISON_9200_BGA (0 << 0)
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#define ARCH_REVISON_9200_PQFP (1 << 0)
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enum at91_soc_type {
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/* 920T */
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AT91_SOC_RM9200,
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/* CAP */
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AT91_SOC_CAP9,
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/* SAM92xx */
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AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263,
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/* SAM9Gxx */
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AT91_SOC_SAM9G10, AT91_SOC_SAM9G20, AT91_SOC_SAM9G45,
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/* SAM9RL */
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AT91_SOC_SAM9RL,
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/* SAM9X5 */
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AT91_SOC_SAM9X5,
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/* Unknown type */
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AT91_SOC_NONE
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};
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enum at91_soc_subtype {
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/* RM9200 */
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AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP,
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/* CAP9 */
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AT91_SOC_CAP9_REV_B, AT91_SOC_CAP9_REV_C,
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/* SAM9260 */
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AT91_SOC_SAM9XE,
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/* SAM9G45 */
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AT91_SOC_SAM9G45ES, AT91_SOC_SAM9M10, AT91_SOC_SAM9G46, AT91_SOC_SAM9M11,
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/* SAM9X5 */
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AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35,
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AT91_SOC_SAM9G25, AT91_SOC_SAM9X25,
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/* Unknown subtype */
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AT91_SOC_SUBTYPE_NONE
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};
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struct at91_socinfo {
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unsigned int type, subtype;
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unsigned int cidr, exid;
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};
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extern struct at91_socinfo at91_soc_initdata;
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const char *at91_get_soc_type(struct at91_socinfo *c);
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const char *at91_get_soc_subtype(struct at91_socinfo *c);
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static inline int at91_soc_is_detected(void)
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{
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return at91_soc_initdata.type != AT91_SOC_NONE;
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}
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#ifdef CONFIG_ARCH_AT91RM9200
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#define cpu_is_at91rm9200() (at91_soc_initdata.type == AT91_SOC_RM9200)
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#define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA)
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#define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP)
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#else
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#define cpu_is_at91rm9200() (0)
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#define cpu_is_at91rm9200_bga() (0)
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#define cpu_is_at91rm9200_pqfp() (0)
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#endif
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#ifdef CONFIG_ARCH_AT91SAM9260
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#define cpu_is_at91sam9xe() (at91_soc_initdata.subtype == AT91_SOC_SAM9XE)
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#define cpu_is_at91sam9260() (at91_soc_initdata.type == AT91_SOC_SAM9260)
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#else
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#define cpu_is_at91sam9xe() (0)
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#define cpu_is_at91sam9260() (0)
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#endif
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#ifdef CONFIG_ARCH_AT91SAM9G20
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#define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20)
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#else
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#define cpu_is_at91sam9g20() (0)
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#endif
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#ifdef CONFIG_ARCH_AT91SAM9261
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#define cpu_is_at91sam9261() (at91_soc_initdata.type == AT91_SOC_SAM9261)
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#else
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#define cpu_is_at91sam9261() (0)
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#endif
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#ifdef CONFIG_ARCH_AT91SAM9G10
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#define cpu_is_at91sam9g10() (at91_soc_initdata.type == AT91_SOC_SAM9G10)
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#else
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#define cpu_is_at91sam9g10() (0)
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#endif
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#ifdef CONFIG_ARCH_AT91SAM9263
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#define cpu_is_at91sam9263() (at91_soc_initdata.type == AT91_SOC_SAM9263)
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#else
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#define cpu_is_at91sam9263() (0)
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#endif
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#ifdef CONFIG_ARCH_AT91SAM9RL
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#define cpu_is_at91sam9rl() (at91_soc_initdata.type == AT91_SOC_SAM9RL)
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#else
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#define cpu_is_at91sam9rl() (0)
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#endif
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#ifdef CONFIG_ARCH_AT91SAM9G45
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#define cpu_is_at91sam9g45() (at91_soc_initdata.type == AT91_SOC_SAM9G45)
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#define cpu_is_at91sam9g45es() (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES)
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#define cpu_is_at91sam9m10() (at91_soc_initdata.subtype == AT91_SOC_SAM9M10)
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#define cpu_is_at91sam9g46() (at91_soc_initdata.subtype == AT91_SOC_SAM9G46)
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#define cpu_is_at91sam9m11() (at91_soc_initdata.subtype == AT91_SOC_SAM9M11)
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#else
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#define cpu_is_at91sam9g45() (0)
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#define cpu_is_at91sam9g45es() (0)
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#define cpu_is_at91sam9m10() (0)
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#define cpu_is_at91sam9g46() (0)
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#define cpu_is_at91sam9m11() (0)
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#endif
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#ifdef CONFIG_ARCH_AT91SAM9X5
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#define cpu_is_at91sam9x5() (at91_soc_initdata.type == AT91_SOC_SAM9X5)
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#define cpu_is_at91sam9g15() (at91_soc_initdata.subtype == AT91_SOC_SAM9G15)
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#define cpu_is_at91sam9g35() (at91_soc_initdata.subtype == AT91_SOC_SAM9G35)
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#define cpu_is_at91sam9x35() (at91_soc_initdata.subtype == AT91_SOC_SAM9X35)
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#define cpu_is_at91sam9g25() (at91_soc_initdata.subtype == AT91_SOC_SAM9G25)
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#define cpu_is_at91sam9x25() (at91_soc_initdata.subtype == AT91_SOC_SAM9X25)
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#else
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#define cpu_is_at91sam9x5() (0)
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#define cpu_is_at91sam9g15() (0)
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#define cpu_is_at91sam9g35() (0)
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#define cpu_is_at91sam9x35() (0)
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#define cpu_is_at91sam9g25() (0)
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#define cpu_is_at91sam9x25() (0)
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#endif
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#ifdef CONFIG_ARCH_AT91CAP9
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#define cpu_is_at91cap9() (at91_soc_initdata.type == AT91_SOC_CAP9)
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#define cpu_is_at91cap9_revB() (at91_soc_initdata.subtype == AT91_SOC_CAP9_REV_B)
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#define cpu_is_at91cap9_revC() (at91_soc_initdata.subtype == AT91_SOC_CAP9_REV_C)
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#else
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#define cpu_is_at91cap9() (0)
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#define cpu_is_at91cap9_revB() (0)
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#define cpu_is_at91cap9_revC() (0)
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#endif
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/*
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* Since this is ARM, we will never run on any AVR32 CPU. But these
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* definitions may reduce clutter in common drivers.
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*/
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#define cpu_is_at32ap7000() (0)
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#endif /* __MACH_CPU_H__ */
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