linux/drivers/gpu/drm/amd/display/amdgpu_dm
Hersen Wu 09ed6ba43e drm/amdgpu/display: navi1x copy dcn watermark clock settings to smu resume from s3 (v2)
This interface is for dGPU Navi1x. Linux dc-pplib interface depends
 on window driver dc implementation.

 For Navi1x, clock settings of dcn watermarks are fixed. the settings
 should be passed to smu during boot up and resume from s3.
 boot up: dc calculate dcn watermark clock settings within dc_create,
 dcn20_resource_construct, then call pplib functions below to pass
 the settings to smu:
 smu_set_watermarks_for_clock_ranges
 smu_set_watermarks_table
 navi10_set_watermarks_table
 smu_write_watermarks_table

 For Renoir, clock settings of dcn watermark are also fixed values.
 dc has implemented different flow for window driver:
 dc_hardware_init / dc_set_power_state
 dcn10_init_hw
 notify_wm_ranges
 set_wm_ranges

 For Linux
 smu_set_watermarks_for_clock_ranges
 renoir_set_watermarks_table
 smu_write_watermarks_table

 dc_hardware_init -> amdgpu_dm_init
 dc_set_power_state --> dm_resume

 therefore, linux dc-pplib interface of navi10/12/14 is different
 from that of Renoir.

v2: add missing unlock in error case

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-05 09:42:08 -05:00
..
amdgpu_dm_color.c drm/amd/display: Free gamma after calculating legacy transfer function 2019-10-25 16:50:07 -04:00
amdgpu_dm_crc.c drm/amd/display: Added pixel dynamic expansion control. 2019-10-10 19:24:26 -05:00
amdgpu_dm_crc.h drm/amd/display: Split out DC programming for CRC capture 2019-08-21 22:18:25 -05:00
amdgpu_dm_debugfs.c drm/amd/display: add color space option when sending link test pattern 2019-11-19 10:12:52 -05:00
amdgpu_dm_debugfs.h amdgpu_dm: no need to check return value of debugfs_create functions 2019-06-13 13:59:49 -05:00
amdgpu_dm_hdcp.c drm/amd/display: Fix HW/SW state mismatch 2020-02-04 10:37:51 -05:00
amdgpu_dm_hdcp.h drm/amd/display: add force Type0/1 flag 2019-11-19 10:12:53 -05:00
amdgpu_dm_helpers.c drm/amd/dm/mst: Ignore payload update failures 2020-02-04 23:30:39 -05:00
amdgpu_dm_irq.c drm/amd: use list_for_each_entry for list iteration. 2020-01-07 12:04:16 -05:00
amdgpu_dm_irq.h
amdgpu_dm_mst_types.c drm/amd/display: Clear link settings on MST disable connector 2020-03-05 09:42:08 -05:00
amdgpu_dm_mst_types.h drm/amdgpu/display: protect new DSC code with CONFIG_DRM_AMD_DC_DCN 2020-01-09 18:07:48 -05:00
amdgpu_dm_pp_smu.c drm/amd/display: add default clocks if not able to fetch them 2019-11-26 12:19:08 -05:00
amdgpu_dm_services.c drm/amd: drop use of drmP.h in display/ 2019-06-10 23:00:20 +02:00
amdgpu_dm_trace.h
amdgpu_dm.c drm/amdgpu/display: navi1x copy dcn watermark clock settings to smu resume from s3 (v2) 2020-03-05 09:42:08 -05:00
amdgpu_dm.h drm/amd/display: Validate DSC caps on MST endpoints 2020-01-09 18:07:47 -05:00
Makefile drm/amd/display: Create amdgpu_dm_hdcp 2019-10-03 09:10:58 -05:00