forked from Minki/linux
09d4993cf5
DRA72-evm has a 256MB 16-bit wide NAND chip. Add pinmux and NAND node. The NAND chips 'Chip select' and 'Write protect' can be controlled using DIP Switch SW5. To use NAND, the switch must be configured like so: SW5.1 (NAND_SELn) = ON (LOW) SW5.9 (GPMC_WPN) = OFF (HIGH) Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
260 lines
6.4 KiB
Plaintext
260 lines
6.4 KiB
Plaintext
/*
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* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "dra72x.dtsi"
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/ {
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model = "TI DRA722";
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compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
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memory {
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device_type = "memory";
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reg = <0x80000000 0x40000000>; /* 1024 MB */
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};
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};
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&dra7_pmx_core {
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i2c1_pins: pinmux_i2c1_pins {
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pinctrl-single,pins = <
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0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
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0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
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>;
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};
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nand_default: nand_default {
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pinctrl-single,pins = <
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0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
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0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
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0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
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0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
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0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
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0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
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0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
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0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
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0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
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0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
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0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
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0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
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0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
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0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
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0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
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0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
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0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
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0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
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0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
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0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
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0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
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0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
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>;
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};
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};
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&i2c1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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clock-frequency = <400000>;
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tps65917: tps65917@58 {
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compatible = "ti,tps65917";
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reg = <0x58>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
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interrupt-parent = <&gic>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,system-power-controller;
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tps65917_pmic {
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compatible = "ti,tps65917-pmic";
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regulators {
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smps1_reg: smps1 {
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/* VDD_MPU */
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regulator-name = "smps1";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1250000>;
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regulator-always-on;
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regulator-boot-on;
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};
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smps2_reg: smps2 {
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/* VDD_CORE */
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regulator-name = "smps2";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1030000>;
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regulator-boot-on;
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regulator-always-on;
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};
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smps3_reg: smps3 {
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/* VDD_GPU IVA DSPEVE */
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regulator-name = "smps3";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1250000>;
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regulator-boot-on;
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regulator-always-on;
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};
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smps4_reg: smps4 {
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/* VDDS1V8 */
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regulator-name = "smps4";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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smps5_reg: smps5 {
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/* VDD_DDR */
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regulator-name = "smps5";
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regulator-min-microvolt = <1350000>;
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regulator-max-microvolt = <1350000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1_reg: ldo1 {
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/* LDO1_OUT --> SDIO */
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regulator-name = "ldo1";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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ldo2_reg: ldo2 {
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/* LDO2_OUT --> TP1017 (UNUSED) */
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regulator-name = "ldo2";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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ldo3_reg: ldo3 {
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/* VDDA_1V8_PHY */
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regulator-name = "ldo3";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo5_reg: ldo5 {
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/* VDDA_1V8_PLL */
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regulator-name = "ldo5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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ldo4_reg: ldo4 {
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/* VDDA_3V_USB: VDDA_USBHS33 */
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regulator-name = "ldo4";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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};
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};
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};
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};
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&uart1 {
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status = "okay";
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};
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&elm {
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status = "okay";
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};
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&gpmc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&nand_default>;
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ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
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nand@0,0 {
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/* To use NAND, DIP switch SW5 must be set like so:
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* SW5.1 (NAND_SELn) = ON (LOW)
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* SW5.9 (GPMC_WPN) = OFF (HIGH)
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*/
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reg = <0 0 4>; /* device IO registers */
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ti,nand-ecc-opt = "bch8";
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ti,elm-id = <&elm>;
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nand-bus-width = <16>;
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gpmc,device-width = <2>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <80>;
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gpmc,cs-wr-off-ns = <80>;
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gpmc,adv-on-ns = <0>;
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gpmc,adv-rd-off-ns = <60>;
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gpmc,adv-wr-off-ns = <60>;
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gpmc,we-on-ns = <10>;
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gpmc,we-off-ns = <50>;
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gpmc,oe-on-ns = <4>;
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gpmc,oe-off-ns = <40>;
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gpmc,access-ns = <40>;
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gpmc,wr-access-ns = <80>;
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gpmc,rd-cycle-ns = <80>;
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gpmc,wr-cycle-ns = <80>;
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,wr-data-mux-bus-ns = <0>;
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/* MTD partition table */
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/* All SPL-* partitions are sized to minimal length
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* which can be independently programmable. For
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* NAND flash this is equal to size of erase-block */
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "NAND.SPL";
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reg = <0x00000000 0x000020000>;
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};
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partition@1 {
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label = "NAND.SPL.backup1";
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reg = <0x00020000 0x00020000>;
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};
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partition@2 {
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label = "NAND.SPL.backup2";
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reg = <0x00040000 0x00020000>;
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};
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partition@3 {
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label = "NAND.SPL.backup3";
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reg = <0x00060000 0x00020000>;
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};
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partition@4 {
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label = "NAND.u-boot-spl-os";
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reg = <0x00080000 0x00040000>;
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};
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partition@5 {
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label = "NAND.u-boot";
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reg = <0x000c0000 0x00100000>;
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};
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partition@6 {
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label = "NAND.u-boot-env";
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reg = <0x001c0000 0x00020000>;
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};
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partition@7 {
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label = "NAND.u-boot-env.backup1";
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reg = <0x001e0000 0x00020000>;
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};
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partition@8 {
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label = "NAND.kernel";
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reg = <0x00200000 0x00800000>;
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};
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partition@9 {
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label = "NAND.file-system";
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reg = <0x00a00000 0x0f600000>;
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};
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};
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};
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