forked from Minki/linux
0988a7a1a9
Previous init path was based on old specs from old driver. Update it as much as possible leaving some TODOs for not implemented functions. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
753 lines
22 KiB
C
753 lines
22 KiB
C
/*
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Broadcom B43 wireless driver
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IEEE 802.11n PHY support
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Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING. If not, write to
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the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
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Boston, MA 02110-1301, USA.
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*/
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#include <linux/delay.h>
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#include <linux/types.h>
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#include "b43.h"
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#include "phy_n.h"
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#include "tables_nphy.h"
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struct nphy_txgains {
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u16 txgm[2];
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u16 pga[2];
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u16 pad[2];
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u16 ipa[2];
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};
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struct nphy_iqcal_params {
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u16 txgm;
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u16 pga;
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u16 pad;
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u16 ipa;
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u16 cal_gain;
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u16 ncorr[5];
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};
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struct nphy_iq_est {
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s32 iq0_prod;
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u32 i0_pwr;
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u32 q0_pwr;
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s32 iq1_prod;
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u32 i1_pwr;
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u32 q1_pwr;
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};
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void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
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{//TODO
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}
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static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
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{//TODO
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}
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static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
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bool ignore_tssi)
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{//TODO
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return B43_TXPWR_RES_DONE;
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}
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static void b43_chantab_radio_upload(struct b43_wldev *dev,
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const struct b43_nphy_channeltab_entry *e)
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{
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b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
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b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
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b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
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b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
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b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
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b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
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b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
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b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
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b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
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b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
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b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
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b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
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b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
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b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
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b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
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b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
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b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
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b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
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b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
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b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
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b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
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b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
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}
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static void b43_chantab_phy_upload(struct b43_wldev *dev,
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const struct b43_nphy_channeltab_entry *e)
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{
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b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
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b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
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b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
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b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
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b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
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b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
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}
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static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
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{
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//TODO
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}
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/* Tune the hardware to a new channel. */
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static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
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{
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const struct b43_nphy_channeltab_entry *tabent;
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tabent = b43_nphy_get_chantabent(dev, channel);
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if (!tabent)
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return -ESRCH;
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//FIXME enable/disable band select upper20 in RXCTL
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if (0 /*FIXME 5Ghz*/)
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b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
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else
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b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
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b43_chantab_radio_upload(dev, tabent);
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udelay(50);
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b43_radio_write16(dev, B2055_VCO_CAL10, 5);
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b43_radio_write16(dev, B2055_VCO_CAL10, 45);
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b43_radio_write16(dev, B2055_VCO_CAL10, 65);
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udelay(300);
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if (0 /*FIXME 5Ghz*/)
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b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
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else
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b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
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b43_chantab_phy_upload(dev, tabent);
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b43_nphy_tx_power_fix(dev);
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return 0;
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}
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static void b43_radio_init2055_pre(struct b43_wldev *dev)
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{
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b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
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~B43_NPHY_RFCTL_CMD_PORFORCE);
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b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
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B43_NPHY_RFCTL_CMD_CHIP0PU |
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B43_NPHY_RFCTL_CMD_OEPORFORCE);
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b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
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B43_NPHY_RFCTL_CMD_PORFORCE);
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}
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static void b43_radio_init2055_post(struct b43_wldev *dev)
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{
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struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
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struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
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int i;
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u16 val;
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b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
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msleep(1);
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if ((sprom->revision != 4) ||
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!(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
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if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
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(binfo->type != 0x46D) ||
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(binfo->rev < 0x41)) {
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b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
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b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
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msleep(1);
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}
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}
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b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
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msleep(1);
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b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
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msleep(1);
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b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
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msleep(1);
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b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
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msleep(1);
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b43_radio_set(dev, B2055_CAL_MISC, 0x1);
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msleep(1);
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b43_radio_set(dev, B2055_CAL_MISC, 0x40);
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msleep(1);
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for (i = 0; i < 100; i++) {
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val = b43_radio_read16(dev, B2055_CAL_COUT2);
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if (val & 0x80)
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break;
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udelay(10);
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}
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msleep(1);
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b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
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msleep(1);
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nphy_channel_switch(dev, dev->phy.channel);
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b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
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b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
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b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
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b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
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}
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/* Initialize a Broadcom 2055 N-radio */
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static void b43_radio_init2055(struct b43_wldev *dev)
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{
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b43_radio_init2055_pre(dev);
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if (b43_status(dev) < B43_STAT_INITIALIZED)
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b2055_upload_inittab(dev, 0, 1);
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else
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b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
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b43_radio_init2055_post(dev);
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}
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void b43_nphy_radio_turn_on(struct b43_wldev *dev)
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{
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b43_radio_init2055(dev);
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}
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void b43_nphy_radio_turn_off(struct b43_wldev *dev)
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{
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b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
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~B43_NPHY_RFCTL_CMD_EN);
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}
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#define ntab_upload(dev, offset, data) do { \
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unsigned int i; \
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for (i = 0; i < (offset##_SIZE); i++) \
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b43_ntab_write(dev, (offset) + i, (data)[i]); \
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} while (0)
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/*
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* Upload the N-PHY tables.
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* http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
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*/
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static void b43_nphy_tables_init(struct b43_wldev *dev)
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{
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if (dev->phy.rev < 3)
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b43_nphy_rev0_1_2_tables_init(dev);
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else
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b43_nphy_rev3plus_tables_init(dev);
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}
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static void b43_nphy_workarounds(struct b43_wldev *dev)
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{
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struct b43_phy *phy = &dev->phy;
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unsigned int i;
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b43_phy_set(dev, B43_NPHY_IQFLIP,
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B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
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if (1 /* FIXME band is 2.4GHz */) {
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b43_phy_set(dev, B43_NPHY_CLASSCTL,
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B43_NPHY_CLASSCTL_CCKEN);
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} else {
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b43_phy_mask(dev, B43_NPHY_CLASSCTL,
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~B43_NPHY_CLASSCTL_CCKEN);
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}
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b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
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b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
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/* Fixup some tables */
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b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
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b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
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b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
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b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
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b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
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b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
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b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
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b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
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b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
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b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
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b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
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b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
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b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
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b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
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//TODO set RF sequence
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/* Set narrowband clip threshold */
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b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
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b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
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/* Set wideband clip 2 threshold */
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b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
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~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
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21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
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b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
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~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
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21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
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/* Set Clip 2 detect */
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b43_phy_set(dev, B43_NPHY_C1_CGAINI,
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B43_NPHY_C1_CGAINI_CL2DETECT);
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b43_phy_set(dev, B43_NPHY_C2_CGAINI,
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B43_NPHY_C2_CGAINI_CL2DETECT);
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if (0 /*FIXME*/) {
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/* Set dwell lengths */
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b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
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b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
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b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
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b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
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/* Set gain backoff */
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b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
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~B43_NPHY_C1_CGAINI_GAINBKOFF,
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1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
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b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
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~B43_NPHY_C2_CGAINI_GAINBKOFF,
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1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
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/* Set HPVGA2 index */
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b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
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~B43_NPHY_C1_INITGAIN_HPVGA2,
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6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
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b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
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~B43_NPHY_C2_INITGAIN_HPVGA2,
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6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
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//FIXME verify that the specs really mean to use autoinc here.
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for (i = 0; i < 3; i++)
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b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
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}
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/* Set minimum gain value */
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b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
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~B43_NPHY_C1_MINGAIN,
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23 << B43_NPHY_C1_MINGAIN_SHIFT);
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b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
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~B43_NPHY_C2_MINGAIN,
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23 << B43_NPHY_C2_MINGAIN_SHIFT);
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if (phy->rev < 2) {
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b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
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~B43_NPHY_SCRAM_SIGCTL_SCM);
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}
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/* Set phase track alpha and beta */
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b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
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b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
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b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
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b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
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b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
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b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
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}
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static void b43_nphy_reset_cca(struct b43_wldev *dev)
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{
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u16 bbcfg;
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ssb_write32(dev->dev, SSB_TMSLOW,
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ssb_read32(dev->dev, SSB_TMSLOW) | SSB_TMSLOW_FGC);
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bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
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b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTCCA);
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b43_phy_write(dev, B43_NPHY_BBCFG,
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bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
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ssb_write32(dev->dev, SSB_TMSLOW,
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ssb_read32(dev->dev, SSB_TMSLOW) & ~SSB_TMSLOW_FGC);
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}
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enum b43_nphy_rf_sequence {
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B43_RFSEQ_RX2TX,
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B43_RFSEQ_TX2RX,
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B43_RFSEQ_RESET2RX,
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B43_RFSEQ_UPDATE_GAINH,
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B43_RFSEQ_UPDATE_GAINL,
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B43_RFSEQ_UPDATE_GAINU,
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};
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static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
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enum b43_nphy_rf_sequence seq)
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{
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static const u16 trigger[] = {
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[B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
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[B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
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[B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
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[B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
|
|
[B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
|
|
[B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
|
|
};
|
|
int i;
|
|
|
|
B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
|
|
|
|
b43_phy_set(dev, B43_NPHY_RFSEQMODE,
|
|
B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
|
|
b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
|
|
for (i = 0; i < 200; i++) {
|
|
if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
|
|
goto ok;
|
|
msleep(1);
|
|
}
|
|
b43err(dev->wl, "RF sequence status timeout\n");
|
|
ok:
|
|
b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
|
|
~(B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER));
|
|
}
|
|
|
|
static void b43_nphy_bphy_init(struct b43_wldev *dev)
|
|
{
|
|
unsigned int i;
|
|
u16 val;
|
|
|
|
val = 0x1E1F;
|
|
for (i = 0; i < 14; i++) {
|
|
b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
|
|
val -= 0x202;
|
|
}
|
|
val = 0x3E3F;
|
|
for (i = 0; i < 16; i++) {
|
|
b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
|
|
val -= 0x202;
|
|
}
|
|
b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
|
|
}
|
|
|
|
/* RSSI Calibration */
|
|
static void b43_nphy_rssi_cal(struct b43_wldev *dev, u8 type)
|
|
{
|
|
//TODO
|
|
}
|
|
|
|
/*
|
|
* Init N-PHY
|
|
* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
|
|
*/
|
|
int b43_phy_initn(struct b43_wldev *dev)
|
|
{
|
|
struct ssb_bus *bus = dev->dev->bus;
|
|
struct b43_phy *phy = &dev->phy;
|
|
struct b43_phy_n *nphy = phy->n;
|
|
u8 tx_pwr_state;
|
|
struct nphy_txgains target;
|
|
u16 tmp;
|
|
enum ieee80211_band tmp2;
|
|
bool do_rssi_cal;
|
|
|
|
u16 clip[2];
|
|
bool do_cal = false;
|
|
|
|
if ((dev->phy.rev >= 3) &&
|
|
(bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
|
|
(b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
|
|
chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
|
|
}
|
|
nphy->deaf_count = 0;
|
|
b43_nphy_tables_init(dev);
|
|
nphy->crsminpwr_adjusted = false;
|
|
nphy->noisevars_adjusted = false;
|
|
|
|
/* Clear all overrides */
|
|
if (dev->phy.rev >= 3) {
|
|
b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
|
|
b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
|
|
b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
|
|
b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
|
|
} else {
|
|
b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
|
|
}
|
|
b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
|
|
b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
|
|
if (dev->phy.rev < 6) {
|
|
b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
|
|
b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
|
|
}
|
|
b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
|
|
~(B43_NPHY_RFSEQMODE_CAOVER |
|
|
B43_NPHY_RFSEQMODE_TROVER));
|
|
if (dev->phy.rev >= 3)
|
|
b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
|
|
b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
|
|
|
|
if (dev->phy.rev <= 2) {
|
|
tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
|
|
b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
|
|
~B43_NPHY_BPHY_CTL3_SCALE,
|
|
tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
|
|
}
|
|
b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
|
|
b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
|
|
|
|
if (bus->sprom.boardflags2_lo & 0x100 ||
|
|
(bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
|
|
bus->boardinfo.type == 0x8B))
|
|
b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
|
|
else
|
|
b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
|
|
b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
|
|
b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
|
|
b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
|
|
|
|
/* TODO MIMO-Config */
|
|
/* TODO Update TX/RX chain */
|
|
|
|
if (phy->rev < 2) {
|
|
b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
|
|
b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
|
|
}
|
|
|
|
tmp2 = b43_current_band(dev->wl);
|
|
if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
|
|
(nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
|
|
b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
|
|
b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
|
|
nphy->papd_epsilon_offset[0] << 7);
|
|
b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
|
|
b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
|
|
nphy->papd_epsilon_offset[1] << 7);
|
|
/* TODO N PHY IPA Set TX Dig Filters */
|
|
} else if (phy->rev >= 5) {
|
|
/* TODO N PHY Ext PA Set TX Dig Filters */
|
|
}
|
|
|
|
b43_nphy_workarounds(dev);
|
|
|
|
/* Reset CCA, in init code it differs a little from standard way */
|
|
/* b43_nphy_bmac_clock_fgc(dev, 1); */
|
|
tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
|
|
b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
|
|
b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
|
|
/* b43_nphy_bmac_clock_fgc(dev, 0); */
|
|
|
|
/* TODO N PHY MAC PHY Clock Set with argument 1 */
|
|
|
|
/* b43_nphy_pa_override(dev, false); */
|
|
b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
|
|
b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
|
|
/* b43_nphy_pa_override(dev, true); */
|
|
|
|
/* b43_nphy_classifier(dev, 0, 0); */
|
|
/* b43_nphy_read_clip_detection(dev, clip); */
|
|
tx_pwr_state = nphy->txpwrctrl;
|
|
/* TODO N PHY TX power control with argument 0
|
|
(turning off power control) */
|
|
/* TODO Fix the TX Power Settings */
|
|
/* TODO N PHY TX Power Control Idle TSSI */
|
|
/* TODO N PHY TX Power Control Setup */
|
|
|
|
if (phy->rev >= 3) {
|
|
/* TODO */
|
|
} else {
|
|
/* TODO Write an N PHY table with ID 26, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
|
|
/* TODO Write an N PHY table with ID 27, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
|
|
}
|
|
|
|
if (nphy->phyrxchain != 3)
|
|
;/* TODO N PHY RX Core Set State with phyrxchain as argument */
|
|
if (nphy->mphase_cal_phase_id > 0)
|
|
;/* TODO PHY Periodic Calibration Multi-Phase Restart */
|
|
|
|
do_rssi_cal = false;
|
|
if (phy->rev >= 3) {
|
|
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
|
|
do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
|
|
else
|
|
do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
|
|
|
|
if (do_rssi_cal)
|
|
;/* b43_nphy_rssi_cal(dev); */
|
|
else
|
|
;/* b43_nphy_restore_rssi_cal(dev); */
|
|
} else {
|
|
/* b43_nphy_rssi_cal(dev); */
|
|
}
|
|
|
|
if (!((nphy->measure_hold & 0x6) != 0)) {
|
|
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
|
|
do_cal = (nphy->iqcal_chanspec_2G == 0);
|
|
else
|
|
do_cal = (nphy->iqcal_chanspec_5G == 0);
|
|
|
|
if (nphy->mute)
|
|
do_cal = false;
|
|
|
|
if (do_cal) {
|
|
/* target = b43_nphy_get_tx_gains(dev); */
|
|
|
|
if (nphy->antsel_type == 2)
|
|
;/*TODO NPHY Superswitch Init with argument 1*/
|
|
if (nphy->perical != 2) {
|
|
/* b43_nphy_rssi_cal(dev); */
|
|
if (phy->rev >= 3) {
|
|
nphy->cal_orig_pwr_idx[0] =
|
|
nphy->txpwrindex[0].index_internal;
|
|
nphy->cal_orig_pwr_idx[1] =
|
|
nphy->txpwrindex[1].index_internal;
|
|
/* TODO N PHY Pre Calibrate TX Gain */
|
|
/*target = b43_nphy_get_tx_gains(dev)*/
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
|
|
if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
|
|
Call N PHY Save Cal
|
|
else if (nphy->mphase_cal_phase_id == 0)
|
|
N PHY Periodic Calibration with argument 3
|
|
} else {
|
|
b43_nphy_restore_cal(dev);
|
|
}
|
|
*/
|
|
|
|
/* b43_nphy_tx_pwr_ctrl_coef_setup(dev); */
|
|
/* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
|
|
b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
|
|
b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
|
|
if (phy->rev >= 3 && phy->rev <= 6)
|
|
b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
|
|
/* b43_nphy_tx_lp_fbw(dev); */
|
|
/* TODO N PHY Spur Workaround */
|
|
|
|
b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
|
|
return 0;
|
|
}
|
|
|
|
static int b43_nphy_op_allocate(struct b43_wldev *dev)
|
|
{
|
|
struct b43_phy_n *nphy;
|
|
|
|
nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
|
|
if (!nphy)
|
|
return -ENOMEM;
|
|
dev->phy.n = nphy;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
|
|
{
|
|
struct b43_phy *phy = &dev->phy;
|
|
struct b43_phy_n *nphy = phy->n;
|
|
|
|
memset(nphy, 0, sizeof(*nphy));
|
|
|
|
//TODO init struct b43_phy_n
|
|
}
|
|
|
|
static void b43_nphy_op_free(struct b43_wldev *dev)
|
|
{
|
|
struct b43_phy *phy = &dev->phy;
|
|
struct b43_phy_n *nphy = phy->n;
|
|
|
|
kfree(nphy);
|
|
phy->n = NULL;
|
|
}
|
|
|
|
static int b43_nphy_op_init(struct b43_wldev *dev)
|
|
{
|
|
return b43_phy_initn(dev);
|
|
}
|
|
|
|
static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
|
|
{
|
|
#if B43_DEBUG
|
|
if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
|
|
/* OFDM registers are onnly available on A/G-PHYs */
|
|
b43err(dev->wl, "Invalid OFDM PHY access at "
|
|
"0x%04X on N-PHY\n", offset);
|
|
dump_stack();
|
|
}
|
|
if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
|
|
/* Ext-G registers are only available on G-PHYs */
|
|
b43err(dev->wl, "Invalid EXT-G PHY access at "
|
|
"0x%04X on N-PHY\n", offset);
|
|
dump_stack();
|
|
}
|
|
#endif /* B43_DEBUG */
|
|
}
|
|
|
|
static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
|
|
{
|
|
check_phyreg(dev, reg);
|
|
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
|
|
return b43_read16(dev, B43_MMIO_PHY_DATA);
|
|
}
|
|
|
|
static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
|
|
{
|
|
check_phyreg(dev, reg);
|
|
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
|
|
b43_write16(dev, B43_MMIO_PHY_DATA, value);
|
|
}
|
|
|
|
static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
|
|
{
|
|
/* Register 1 is a 32-bit register. */
|
|
B43_WARN_ON(reg == 1);
|
|
/* N-PHY needs 0x100 for read access */
|
|
reg |= 0x100;
|
|
|
|
b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
|
|
return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
|
|
}
|
|
|
|
static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
|
|
{
|
|
/* Register 1 is a 32-bit register. */
|
|
B43_WARN_ON(reg == 1);
|
|
|
|
b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
|
|
b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
|
|
}
|
|
|
|
static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
|
|
bool blocked)
|
|
{//TODO
|
|
}
|
|
|
|
static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
|
|
{
|
|
b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
|
|
on ? 0 : 0x7FFF);
|
|
}
|
|
|
|
static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
|
|
unsigned int new_channel)
|
|
{
|
|
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
|
|
if ((new_channel < 1) || (new_channel > 14))
|
|
return -EINVAL;
|
|
} else {
|
|
if (new_channel > 200)
|
|
return -EINVAL;
|
|
}
|
|
|
|
return nphy_channel_switch(dev, new_channel);
|
|
}
|
|
|
|
static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
|
|
{
|
|
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
|
|
return 1;
|
|
return 36;
|
|
}
|
|
|
|
const struct b43_phy_operations b43_phyops_n = {
|
|
.allocate = b43_nphy_op_allocate,
|
|
.free = b43_nphy_op_free,
|
|
.prepare_structs = b43_nphy_op_prepare_structs,
|
|
.init = b43_nphy_op_init,
|
|
.phy_read = b43_nphy_op_read,
|
|
.phy_write = b43_nphy_op_write,
|
|
.radio_read = b43_nphy_op_radio_read,
|
|
.radio_write = b43_nphy_op_radio_write,
|
|
.software_rfkill = b43_nphy_op_software_rfkill,
|
|
.switch_analog = b43_nphy_op_switch_analog,
|
|
.switch_channel = b43_nphy_op_switch_channel,
|
|
.get_default_chan = b43_nphy_op_get_default_chan,
|
|
.recalc_txpower = b43_nphy_op_recalc_txpower,
|
|
.adjust_txpower = b43_nphy_op_adjust_txpower,
|
|
};
|