forked from Minki/linux
e4f6dfa9ef
When programming port decode targets, the algorithm wants to ensure that
two devices are compatible to be programmed as peers beneath a given
port. A compatible peer is a target that shares the same dport, and
where that target's interleave position also routes it to the same
dport. Compatibility is determined by the device's interleave position
being >= to distance. For example, if a given dport can only map every
Nth position then positions less than N away from the last target
programmed are incompatible.
The @distance for the host-bridge's cxl_port in a simple dual-ported
host-bridge configuration with 2 direct-attached devices is 1, i.e. An
x2 region divided by 2 dports to reach 2 region targets.
An x4 region under an x2 host-bridge would need 2 intervening switches
where the @distance at the host bridge level is 2 (x4 region divided by
2 switches to reach 4 devices).
However, the distance between peers underneath a single ported
host-bridge is always zero because there is no limit to the number of
devices that can be mapped. In other words, there are no decoders to
program in a passthrough, all descendants are mapped and distance only
starts matters for the intervening descendant ports of the passthrough
port.
Add tracking for the number of dports mapped to a port, and use that to
detect the passthrough case for calculating @distance.
Cc: <stable@vger.kernel.org>
Reported-by: Bobo WL <lmw.bobo@gmail.com>
Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: http://lore.kernel.org/r/20221010172057.00001559@huawei.com
Fixes: 27b3f8d138 ("cxl/region: Program target lists")
Reviewed-by: Vishal Verma <vishal.l.verma@intel.com>
Link: https://lore.kernel.org/r/166752185440.947915.6617495912508299445.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
666 lines
21 KiB
C
666 lines
21 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2020 Intel Corporation. */
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#ifndef __CXL_H__
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#define __CXL_H__
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#include <linux/libnvdimm.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/log2.h>
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#include <linux/io.h>
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/**
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* DOC: cxl objects
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*
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* The CXL core objects like ports, decoders, and regions are shared
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* between the subsystem drivers cxl_acpi, cxl_pci, and core drivers
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* (port-driver, region-driver, nvdimm object-drivers... etc).
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*/
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/* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */
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#define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K
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/* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/
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#define CXL_CM_OFFSET 0x1000
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#define CXL_CM_CAP_HDR_OFFSET 0x0
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#define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0)
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#define CM_CAP_HDR_CAP_ID 1
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#define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16)
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#define CM_CAP_HDR_CAP_VERSION 1
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#define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20)
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#define CM_CAP_HDR_CACHE_MEM_VERSION 1
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#define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24)
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#define CXL_CM_CAP_PTR_MASK GENMASK(31, 20)
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#define CXL_CM_CAP_CAP_ID_HDM 0x5
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#define CXL_CM_CAP_CAP_HDM_VERSION 1
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/* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */
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#define CXL_HDM_DECODER_CAP_OFFSET 0x0
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#define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0)
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#define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4)
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#define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8)
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#define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9)
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#define CXL_HDM_DECODER_CTRL_OFFSET 0x4
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#define CXL_HDM_DECODER_ENABLE BIT(1)
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#define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10)
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#define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14)
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#define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18)
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#define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c)
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#define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20)
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#define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0)
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#define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4)
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#define CXL_HDM_DECODER0_CTRL_LOCK BIT(8)
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#define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9)
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#define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10)
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#define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11)
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#define CXL_HDM_DECODER0_CTRL_TYPE BIT(12)
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#define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24)
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#define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28)
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#define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i)
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#define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i)
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static inline int cxl_hdm_decoder_count(u32 cap_hdr)
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{
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int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr);
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return val ? val * 2 : 1;
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}
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/* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */
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static inline int cxl_to_granularity(u16 ig, unsigned int *val)
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{
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if (ig > 6)
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return -EINVAL;
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*val = 256 << ig;
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return 0;
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}
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/* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */
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static inline int cxl_to_ways(u8 eniw, unsigned int *val)
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{
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switch (eniw) {
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case 0 ... 4:
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*val = 1 << eniw;
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break;
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case 8 ... 10:
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*val = 3 << (eniw - 8);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static inline int granularity_to_cxl(int g, u16 *ig)
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{
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if (g > SZ_16K || g < 256 || !is_power_of_2(g))
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return -EINVAL;
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*ig = ilog2(g) - 8;
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return 0;
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}
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static inline int ways_to_cxl(unsigned int ways, u8 *iw)
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{
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if (ways > 16)
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return -EINVAL;
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if (is_power_of_2(ways)) {
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*iw = ilog2(ways);
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return 0;
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}
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if (ways % 3)
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return -EINVAL;
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ways /= 3;
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if (!is_power_of_2(ways))
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return -EINVAL;
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*iw = ilog2(ways) + 8;
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return 0;
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}
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/* CXL 2.0 8.2.8.1 Device Capabilities Array Register */
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#define CXLDEV_CAP_ARRAY_OFFSET 0x0
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#define CXLDEV_CAP_ARRAY_CAP_ID 0
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#define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0)
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#define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32)
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/* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */
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#define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0)
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/* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */
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#define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1
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#define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2
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#define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3
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#define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000
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/* CXL 2.0 8.2.8.4 Mailbox Registers */
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#define CXLDEV_MBOX_CAPS_OFFSET 0x00
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#define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0)
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#define CXLDEV_MBOX_CTRL_OFFSET 0x04
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#define CXLDEV_MBOX_CTRL_DOORBELL BIT(0)
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#define CXLDEV_MBOX_CMD_OFFSET 0x08
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#define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0)
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#define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16)
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#define CXLDEV_MBOX_STATUS_OFFSET 0x10
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#define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32)
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#define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18
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#define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20
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/*
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* Using struct_group() allows for per register-block-type helper routines,
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* without requiring block-type agnostic code to include the prefix.
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*/
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struct cxl_regs {
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/*
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* Common set of CXL Component register block base pointers
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* @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure
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*/
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struct_group_tagged(cxl_component_regs, component,
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void __iomem *hdm_decoder;
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);
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/*
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* Common set of CXL Device register block base pointers
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* @status: CXL 2.0 8.2.8.3 Device Status Registers
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* @mbox: CXL 2.0 8.2.8.4 Mailbox Registers
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* @memdev: CXL 2.0 8.2.8.5 Memory Device Registers
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*/
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struct_group_tagged(cxl_device_regs, device_regs,
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void __iomem *status, *mbox, *memdev;
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);
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};
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struct cxl_reg_map {
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bool valid;
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unsigned long offset;
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unsigned long size;
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};
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struct cxl_component_reg_map {
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struct cxl_reg_map hdm_decoder;
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};
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struct cxl_device_reg_map {
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struct cxl_reg_map status;
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struct cxl_reg_map mbox;
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struct cxl_reg_map memdev;
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};
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/**
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* struct cxl_register_map - DVSEC harvested register block mapping parameters
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* @base: virtual base of the register-block-BAR + @block_offset
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* @block_offset: offset to start of register block in @barno
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* @reg_type: see enum cxl_regloc_type
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* @barno: PCI BAR number containing the register block
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* @component_map: cxl_reg_map for component registers
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* @device_map: cxl_reg_maps for device registers
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*/
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struct cxl_register_map {
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void __iomem *base;
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u64 block_offset;
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u8 reg_type;
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u8 barno;
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union {
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struct cxl_component_reg_map component_map;
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struct cxl_device_reg_map device_map;
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};
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};
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void cxl_probe_component_regs(struct device *dev, void __iomem *base,
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struct cxl_component_reg_map *map);
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void cxl_probe_device_regs(struct device *dev, void __iomem *base,
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struct cxl_device_reg_map *map);
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int cxl_map_component_regs(struct pci_dev *pdev,
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struct cxl_component_regs *regs,
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struct cxl_register_map *map);
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int cxl_map_device_regs(struct pci_dev *pdev,
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struct cxl_device_regs *regs,
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struct cxl_register_map *map);
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enum cxl_regloc_type;
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int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
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struct cxl_register_map *map);
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void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
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resource_size_t length);
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#define CXL_RESOURCE_NONE ((resource_size_t) -1)
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#define CXL_TARGET_STRLEN 20
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/*
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* cxl_decoder flags that define the type of memory / devices this
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* decoder supports as well as configuration lock status See "CXL 2.0
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* 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details.
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*/
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#define CXL_DECODER_F_RAM BIT(0)
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#define CXL_DECODER_F_PMEM BIT(1)
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#define CXL_DECODER_F_TYPE2 BIT(2)
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#define CXL_DECODER_F_TYPE3 BIT(3)
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#define CXL_DECODER_F_LOCK BIT(4)
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#define CXL_DECODER_F_ENABLE BIT(5)
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#define CXL_DECODER_F_MASK GENMASK(5, 0)
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enum cxl_decoder_type {
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CXL_DECODER_ACCELERATOR = 2,
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CXL_DECODER_EXPANDER = 3,
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};
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/*
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* Current specification goes up to 8, double that seems a reasonable
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* software max for the foreseeable future
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*/
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#define CXL_DECODER_MAX_INTERLEAVE 16
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#define CXL_DECODER_MIN_GRANULARITY 256
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/**
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* struct cxl_decoder - Common CXL HDM Decoder Attributes
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* @dev: this decoder's device
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* @id: kernel device name id
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* @hpa_range: Host physical address range mapped by this decoder
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* @interleave_ways: number of cxl_dports in this decode
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* @interleave_granularity: data stride per dport
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* @target_type: accelerator vs expander (type2 vs type3) selector
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* @region: currently assigned region for this decoder
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* @flags: memory type capabilities and locking
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* @commit: device/decoder-type specific callback to commit settings to hw
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* @reset: device/decoder-type specific callback to reset hw settings
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*/
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struct cxl_decoder {
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struct device dev;
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int id;
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struct range hpa_range;
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int interleave_ways;
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int interleave_granularity;
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enum cxl_decoder_type target_type;
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struct cxl_region *region;
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unsigned long flags;
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int (*commit)(struct cxl_decoder *cxld);
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int (*reset)(struct cxl_decoder *cxld);
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};
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/*
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* CXL_DECODER_DEAD prevents endpoints from being reattached to regions
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* while cxld_unregister() is running
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*/
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enum cxl_decoder_mode {
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CXL_DECODER_NONE,
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CXL_DECODER_RAM,
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CXL_DECODER_PMEM,
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CXL_DECODER_MIXED,
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CXL_DECODER_DEAD,
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};
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/**
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* struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder
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* @cxld: base cxl_decoder_object
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* @dpa_res: actively claimed DPA span of this decoder
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* @skip: offset into @dpa_res where @cxld.hpa_range maps
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* @mode: which memory type / access-mode-partition this decoder targets
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* @pos: interleave position in @cxld.region
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*/
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struct cxl_endpoint_decoder {
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struct cxl_decoder cxld;
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struct resource *dpa_res;
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resource_size_t skip;
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enum cxl_decoder_mode mode;
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int pos;
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};
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/**
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* struct cxl_switch_decoder - Switch specific CXL HDM Decoder
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* @cxld: base cxl_decoder object
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* @target_lock: coordinate coherent reads of the target list
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* @nr_targets: number of elements in @target
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* @target: active ordered target list in current decoder configuration
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*
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* The 'switch' decoder type represents the decoder instances of cxl_port's that
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* route from the root of a CXL memory decode topology to the endpoints. They
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* come in two flavors, root-level decoders, statically defined by platform
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* firmware, and mid-level decoders, where interleave-granularity,
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* interleave-width, and the target list are mutable.
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*/
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struct cxl_switch_decoder {
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struct cxl_decoder cxld;
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seqlock_t target_lock;
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int nr_targets;
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struct cxl_dport *target[];
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};
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/**
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* struct cxl_root_decoder - Static platform CXL address decoder
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* @res: host / parent resource for region allocations
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* @region_id: region id for next region provisioning event
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* @calc_hb: which host bridge covers the n'th position by granularity
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* @cxlsd: base cxl switch decoder
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*/
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struct cxl_root_decoder {
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struct resource *res;
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atomic_t region_id;
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struct cxl_dport *(*calc_hb)(struct cxl_root_decoder *cxlrd, int pos);
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struct cxl_switch_decoder cxlsd;
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};
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/*
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* enum cxl_config_state - State machine for region configuration
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* @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely
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* @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more
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* changes to interleave_ways or interleave_granularity
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* @CXL_CONFIG_ACTIVE: All targets have been added the region is now
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* active
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* @CXL_CONFIG_RESET_PENDING: see commit_store()
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* @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware
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*/
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enum cxl_config_state {
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CXL_CONFIG_IDLE,
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CXL_CONFIG_INTERLEAVE_ACTIVE,
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CXL_CONFIG_ACTIVE,
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CXL_CONFIG_RESET_PENDING,
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CXL_CONFIG_COMMIT,
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};
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/**
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* struct cxl_region_params - region settings
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* @state: allow the driver to lockdown further parameter changes
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* @uuid: unique id for persistent regions
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* @interleave_ways: number of endpoints in the region
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* @interleave_granularity: capacity each endpoint contributes to a stripe
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* @res: allocated iomem capacity for this region
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* @targets: active ordered targets in current decoder configuration
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* @nr_targets: number of targets
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*
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* State transitions are protected by the cxl_region_rwsem
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*/
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struct cxl_region_params {
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enum cxl_config_state state;
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uuid_t uuid;
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int interleave_ways;
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int interleave_granularity;
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struct resource *res;
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struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE];
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int nr_targets;
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};
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/**
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* struct cxl_region - CXL region
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* @dev: This region's device
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* @id: This region's id. Id is globally unique across all regions
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* @mode: Endpoint decoder allocation / access mode
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* @type: Endpoint decoder target type
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* @params: active + config params for the region
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*/
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struct cxl_region {
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struct device dev;
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int id;
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enum cxl_decoder_mode mode;
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enum cxl_decoder_type type;
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struct cxl_region_params params;
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};
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/**
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* enum cxl_nvdimm_brige_state - state machine for managing bus rescans
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* @CXL_NVB_NEW: Set at bridge create and after cxl_pmem_wq is destroyed
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* @CXL_NVB_DEAD: Set at brige unregistration to preclude async probing
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* @CXL_NVB_ONLINE: Target state after successful ->probe()
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* @CXL_NVB_OFFLINE: Target state after ->remove() or failed ->probe()
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*/
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enum cxl_nvdimm_brige_state {
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CXL_NVB_NEW,
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CXL_NVB_DEAD,
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CXL_NVB_ONLINE,
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CXL_NVB_OFFLINE,
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};
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struct cxl_nvdimm_bridge {
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int id;
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struct device dev;
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|
struct cxl_port *port;
|
|
struct nvdimm_bus *nvdimm_bus;
|
|
struct nvdimm_bus_descriptor nd_desc;
|
|
struct work_struct state_work;
|
|
enum cxl_nvdimm_brige_state state;
|
|
};
|
|
|
|
struct cxl_nvdimm {
|
|
struct device dev;
|
|
struct cxl_memdev *cxlmd;
|
|
struct cxl_nvdimm_bridge *bridge;
|
|
struct xarray pmem_regions;
|
|
};
|
|
|
|
struct cxl_pmem_region_mapping {
|
|
struct cxl_memdev *cxlmd;
|
|
struct cxl_nvdimm *cxl_nvd;
|
|
u64 start;
|
|
u64 size;
|
|
int position;
|
|
};
|
|
|
|
struct cxl_pmem_region {
|
|
struct device dev;
|
|
struct cxl_region *cxlr;
|
|
struct nd_region *nd_region;
|
|
struct cxl_nvdimm_bridge *bridge;
|
|
struct range hpa_range;
|
|
int nr_mappings;
|
|
struct cxl_pmem_region_mapping mapping[];
|
|
};
|
|
|
|
/**
|
|
* struct cxl_port - logical collection of upstream port devices and
|
|
* downstream port devices to construct a CXL memory
|
|
* decode hierarchy.
|
|
* @dev: this port's device
|
|
* @uport: PCI or platform device implementing the upstream port capability
|
|
* @host_bridge: Shortcut to the platform attach point for this port
|
|
* @id: id for port device-name
|
|
* @dports: cxl_dport instances referenced by decoders
|
|
* @endpoints: cxl_ep instances, endpoints that are a descendant of this port
|
|
* @regions: cxl_region_ref instances, regions mapped by this port
|
|
* @parent_dport: dport that points to this port in the parent
|
|
* @decoder_ida: allocator for decoder ids
|
|
* @nr_dports: number of entries in @dports
|
|
* @hdm_end: track last allocated HDM decoder instance for allocation ordering
|
|
* @commit_end: cursor to track highest committed decoder for commit ordering
|
|
* @component_reg_phys: component register capability base address (optional)
|
|
* @dead: last ep has been removed, force port re-creation
|
|
* @depth: How deep this port is relative to the root. depth 0 is the root.
|
|
* @cdat: Cached CDAT data
|
|
* @cdat_available: Should a CDAT attribute be available in sysfs
|
|
*/
|
|
struct cxl_port {
|
|
struct device dev;
|
|
struct device *uport;
|
|
struct device *host_bridge;
|
|
int id;
|
|
struct xarray dports;
|
|
struct xarray endpoints;
|
|
struct xarray regions;
|
|
struct cxl_dport *parent_dport;
|
|
struct ida decoder_ida;
|
|
int nr_dports;
|
|
int hdm_end;
|
|
int commit_end;
|
|
resource_size_t component_reg_phys;
|
|
bool dead;
|
|
unsigned int depth;
|
|
struct cxl_cdat {
|
|
void *table;
|
|
size_t length;
|
|
} cdat;
|
|
bool cdat_available;
|
|
};
|
|
|
|
static inline struct cxl_dport *
|
|
cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev)
|
|
{
|
|
return xa_load(&port->dports, (unsigned long)dport_dev);
|
|
}
|
|
|
|
/**
|
|
* struct cxl_dport - CXL downstream port
|
|
* @dport: PCI bridge or firmware device representing the downstream link
|
|
* @port_id: unique hardware identifier for dport in decoder target list
|
|
* @component_reg_phys: downstream port component registers
|
|
* @port: reference to cxl_port that contains this downstream port
|
|
*/
|
|
struct cxl_dport {
|
|
struct device *dport;
|
|
int port_id;
|
|
resource_size_t component_reg_phys;
|
|
struct cxl_port *port;
|
|
};
|
|
|
|
/**
|
|
* struct cxl_ep - track an endpoint's interest in a port
|
|
* @ep: device that hosts a generic CXL endpoint (expander or accelerator)
|
|
* @dport: which dport routes to this endpoint on @port
|
|
* @next: cxl switch port across the link attached to @dport NULL if
|
|
* attached to an endpoint
|
|
*/
|
|
struct cxl_ep {
|
|
struct device *ep;
|
|
struct cxl_dport *dport;
|
|
struct cxl_port *next;
|
|
};
|
|
|
|
/**
|
|
* struct cxl_region_ref - track a region's interest in a port
|
|
* @port: point in topology to install this reference
|
|
* @decoder: decoder assigned for @region in @port
|
|
* @region: region for this reference
|
|
* @endpoints: cxl_ep references for region members beneath @port
|
|
* @nr_targets_set: track how many targets have been programmed during setup
|
|
* @nr_eps: number of endpoints beneath @port
|
|
* @nr_targets: number of distinct targets needed to reach @nr_eps
|
|
*/
|
|
struct cxl_region_ref {
|
|
struct cxl_port *port;
|
|
struct cxl_decoder *decoder;
|
|
struct cxl_region *region;
|
|
struct xarray endpoints;
|
|
int nr_targets_set;
|
|
int nr_eps;
|
|
int nr_targets;
|
|
};
|
|
|
|
/*
|
|
* The platform firmware device hosting the root is also the top of the
|
|
* CXL port topology. All other CXL ports have another CXL port as their
|
|
* parent and their ->uport / host device is out-of-line of the port
|
|
* ancestry.
|
|
*/
|
|
static inline bool is_cxl_root(struct cxl_port *port)
|
|
{
|
|
return port->uport == port->dev.parent;
|
|
}
|
|
|
|
bool is_cxl_port(struct device *dev);
|
|
struct cxl_port *to_cxl_port(struct device *dev);
|
|
struct pci_bus;
|
|
int devm_cxl_register_pci_bus(struct device *host, struct device *uport,
|
|
struct pci_bus *bus);
|
|
struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port);
|
|
struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
|
|
resource_size_t component_reg_phys,
|
|
struct cxl_dport *parent_dport);
|
|
int devm_cxl_add_endpoint(struct cxl_memdev *cxlmd,
|
|
struct cxl_dport *parent_dport);
|
|
struct cxl_port *find_cxl_root(struct device *dev);
|
|
int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd);
|
|
int cxl_bus_rescan(void);
|
|
struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd,
|
|
struct cxl_dport **dport);
|
|
bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd);
|
|
|
|
struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
|
|
struct device *dport, int port_id,
|
|
resource_size_t component_reg_phys);
|
|
|
|
struct cxl_decoder *to_cxl_decoder(struct device *dev);
|
|
struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev);
|
|
struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev);
|
|
bool is_root_decoder(struct device *dev);
|
|
bool is_endpoint_decoder(struct device *dev);
|
|
struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
|
|
unsigned int nr_targets);
|
|
struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
|
|
unsigned int nr_targets);
|
|
int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map);
|
|
struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port);
|
|
int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map);
|
|
int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld);
|
|
int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint);
|
|
|
|
struct cxl_hdm;
|
|
struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port);
|
|
int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm);
|
|
int devm_cxl_add_passthrough_decoder(struct cxl_port *port);
|
|
|
|
bool is_cxl_region(struct device *dev);
|
|
|
|
extern struct bus_type cxl_bus_type;
|
|
|
|
struct cxl_driver {
|
|
const char *name;
|
|
int (*probe)(struct device *dev);
|
|
void (*remove)(struct device *dev);
|
|
struct device_driver drv;
|
|
int id;
|
|
};
|
|
|
|
static inline struct cxl_driver *to_cxl_drv(struct device_driver *drv)
|
|
{
|
|
return container_of(drv, struct cxl_driver, drv);
|
|
}
|
|
|
|
int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner,
|
|
const char *modname);
|
|
#define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME)
|
|
void cxl_driver_unregister(struct cxl_driver *cxl_drv);
|
|
|
|
#define module_cxl_driver(__cxl_driver) \
|
|
module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister)
|
|
|
|
#define CXL_DEVICE_NVDIMM_BRIDGE 1
|
|
#define CXL_DEVICE_NVDIMM 2
|
|
#define CXL_DEVICE_PORT 3
|
|
#define CXL_DEVICE_ROOT 4
|
|
#define CXL_DEVICE_MEMORY_EXPANDER 5
|
|
#define CXL_DEVICE_REGION 6
|
|
#define CXL_DEVICE_PMEM_REGION 7
|
|
|
|
#define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*")
|
|
#define CXL_MODALIAS_FMT "cxl:t%d"
|
|
|
|
struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev);
|
|
struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host,
|
|
struct cxl_port *port);
|
|
struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev);
|
|
bool is_cxl_nvdimm(struct device *dev);
|
|
bool is_cxl_nvdimm_bridge(struct device *dev);
|
|
int devm_cxl_add_nvdimm(struct device *host, struct cxl_memdev *cxlmd);
|
|
struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct device *dev);
|
|
|
|
#ifdef CONFIG_CXL_REGION
|
|
bool is_cxl_pmem_region(struct device *dev);
|
|
struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev);
|
|
#else
|
|
static inline bool is_cxl_pmem_region(struct device *dev)
|
|
{
|
|
return false;
|
|
}
|
|
static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev)
|
|
{
|
|
return NULL;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Unit test builds overrides this to __weak, find the 'strong' version
|
|
* of these symbols in tools/testing/cxl/.
|
|
*/
|
|
#ifndef __mock
|
|
#define __mock static
|
|
#endif
|
|
|
|
#endif /* __CXL_H__ */
|