08fdf65e37
SAI supports these operation modes: 1) asynchronous mode Both Tx and Rx are set to be asynchronous. 2) synchronous mode (Rx sync with Tx) Tx is set to be asynchronous, Rx is set to be synchronous. 3) synchronous mode (Tx sync with Rx) Rx is set to be asynchronous, Tx is set to be synchronous. 4) synchronous mode (Tx/Rx sync with another SAI's Tx) 5) synchronous mode (Tx/Rx sync with another SAI's Rx) * 4) and 5) are beyond this patch because they are related with another SAI. As the initial version of this SAI driver, it supported 2) as default while the others were totally missing. So this patch just adds supports for 1) and 3). Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
60 lines
2.7 KiB
Plaintext
60 lines
2.7 KiB
Plaintext
Freescale Synchronous Audio Interface (SAI).
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The SAI is based on I2S module that used communicating with audio codecs,
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which provides a synchronous audio interface that supports fullduplex
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serial interfaces with frame synchronization such as I2S, AC97, TDM, and
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codec/DSP interfaces.
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Required properties:
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- compatible: Compatible list, contains "fsl,vf610-sai" or "fsl,imx6sx-sai".
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- reg: Offset and length of the register set for the device.
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- clocks: Must contain an entry for each entry in clock-names.
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- clock-names : Must include the "bus" for register access and "mclk1" "mclk2"
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"mclk3" for bit clock and frame clock providing.
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- dmas : Generic dma devicetree binding as described in
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Documentation/devicetree/bindings/dma/dma.txt.
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- dma-names : Two dmas have to be defined, "tx" and "rx".
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- pinctrl-names: Must contain a "default" entry.
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- pinctrl-NNN: One property must exist for each entry in pinctrl-names.
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See ../pinctrl/pinctrl-bindings.txt for details of the property values.
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- big-endian-regs: If this property is absent, the little endian mode will
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be in use as default, or the big endian mode will be in use for all the
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device registers.
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- big-endian-data: If this property is absent, the little endian mode will
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be in use as default, or the big endian mode will be in use for all the
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fifo data.
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- fsl,sai-synchronous-rx: This is a boolean property. If present, indicating
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that SAI will work in the synchronous mode (sync Tx with Rx) which means
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both the transimitter and receiver will send and receive data by following
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receiver's bit clocks and frame sync clocks.
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- fsl,sai-asynchronous: This is a boolean property. If present, indicating
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that SAI will work in the asynchronous mode, which means both transimitter
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and receiver will send and receive data by following their own bit clocks
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and frame sync clocks separately.
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Note:
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- If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
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default synchronous mode (sync Rx with Tx) will be used, which means both
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transimitter and receiver will send and receive data by following clocks
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of transimitter.
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- fsl,sai-asynchronous will be ignored if fsl,sai-synchronous-rx property is
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already present.
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Example:
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sai2: sai@40031000 {
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compatible = "fsl,vf610-sai";
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reg = <0x40031000 0x1000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai2_1>;
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clocks = <&clks VF610_CLK_PLATFORM_BUS>,
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<&clks VF610_CLK_SAI2>,
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<&clks 0>, <&clks 0>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dma-names = "tx", "rx";
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dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
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<&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
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big-endian-regs;
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big-endian-data;
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};
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