forked from Minki/linux
4b65a5db36
This patch adds the uaccess macros/functions to disable access to user space by setting TTBR0_EL1 to a reserved zeroed page. Since the value written to TTBR0_EL1 must be a physical address, for simplicity this patch introduces a reserved_ttbr0 page at a constant offset from swapper_pg_dir. The uaccess_disable code uses the ttbr1_el1 value adjusted by the reserved_ttbr0 offset. Enabling access to user is done by restoring TTBR0_EL1 with the value from the struct thread_info ttbr0 variable. Interrupts must be disabled during the uaccess_ttbr0_enable code to ensure the atomicity of the thread_info.ttbr0 read and TTBR0_EL1 write. This patch also moves the get_thread_info asm macro from entry.S to assembler.h for reuse in the uaccess_ttbr0_* macros. Cc: Will Deacon <will.deacon@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Kees Cook <keescook@chromium.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
118 lines
4.0 KiB
C
118 lines
4.0 KiB
C
/*
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* Kernel page table mapping
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*
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* Copyright (C) 2015 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_KERNEL_PGTABLE_H
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#define __ASM_KERNEL_PGTABLE_H
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#include <asm/pgtable.h>
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#include <asm/sparsemem.h>
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/*
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* The linear mapping and the start of memory are both 2M aligned (per
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* the arm64 booting.txt requirements). Hence we can use section mapping
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* with 4K (section size = 2M) but not with 16K (section size = 32M) or
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* 64K (section size = 512M).
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*/
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#ifdef CONFIG_ARM64_4K_PAGES
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#define ARM64_SWAPPER_USES_SECTION_MAPS 1
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#else
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#define ARM64_SWAPPER_USES_SECTION_MAPS 0
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#endif
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/*
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* The idmap and swapper page tables need some space reserved in the kernel
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* image. Both require pgd, pud (4 levels only) and pmd tables to (section)
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* map the kernel. With the 64K page configuration, swapper and idmap need to
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* map to pte level. The swapper also maps the FDT (see __create_page_tables
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* for more information). Note that the number of ID map translation levels
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* could be increased on the fly if system RAM is out of reach for the default
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* VA range, so pages required to map highest possible PA are reserved in all
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* cases.
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*/
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#if ARM64_SWAPPER_USES_SECTION_MAPS
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#define SWAPPER_PGTABLE_LEVELS (CONFIG_PGTABLE_LEVELS - 1)
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#define IDMAP_PGTABLE_LEVELS (ARM64_HW_PGTABLE_LEVELS(PHYS_MASK_SHIFT) - 1)
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#else
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#define SWAPPER_PGTABLE_LEVELS (CONFIG_PGTABLE_LEVELS)
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#define IDMAP_PGTABLE_LEVELS (ARM64_HW_PGTABLE_LEVELS(PHYS_MASK_SHIFT))
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#endif
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#define SWAPPER_DIR_SIZE (SWAPPER_PGTABLE_LEVELS * PAGE_SIZE)
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#define IDMAP_DIR_SIZE (IDMAP_PGTABLE_LEVELS * PAGE_SIZE)
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#ifdef CONFIG_ARM64_SW_TTBR0_PAN
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#define RESERVED_TTBR0_SIZE (PAGE_SIZE)
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#else
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#define RESERVED_TTBR0_SIZE (0)
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#endif
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/* Initial memory map size */
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#if ARM64_SWAPPER_USES_SECTION_MAPS
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#define SWAPPER_BLOCK_SHIFT SECTION_SHIFT
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#define SWAPPER_BLOCK_SIZE SECTION_SIZE
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#define SWAPPER_TABLE_SHIFT PUD_SHIFT
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#else
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#define SWAPPER_BLOCK_SHIFT PAGE_SHIFT
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#define SWAPPER_BLOCK_SIZE PAGE_SIZE
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#define SWAPPER_TABLE_SHIFT PMD_SHIFT
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#endif
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/* The size of the initial kernel direct mapping */
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#define SWAPPER_INIT_MAP_SIZE (_AC(1, UL) << SWAPPER_TABLE_SHIFT)
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/*
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* Initial memory map attributes.
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*/
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#define SWAPPER_PTE_FLAGS (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
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#define SWAPPER_PMD_FLAGS (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
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#if ARM64_SWAPPER_USES_SECTION_MAPS
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#define SWAPPER_MM_MMUFLAGS (PMD_ATTRINDX(MT_NORMAL) | SWAPPER_PMD_FLAGS)
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#else
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#define SWAPPER_MM_MMUFLAGS (PTE_ATTRINDX(MT_NORMAL) | SWAPPER_PTE_FLAGS)
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#endif
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/*
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* To make optimal use of block mappings when laying out the linear
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* mapping, round down the base of physical memory to a size that can
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* be mapped efficiently, i.e., either PUD_SIZE (4k granule) or PMD_SIZE
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* (64k granule), or a multiple that can be mapped using contiguous bits
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* in the page tables: 32 * PMD_SIZE (16k granule)
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*/
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#if defined(CONFIG_ARM64_4K_PAGES)
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#define ARM64_MEMSTART_SHIFT PUD_SHIFT
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#elif defined(CONFIG_ARM64_16K_PAGES)
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#define ARM64_MEMSTART_SHIFT (PMD_SHIFT + 5)
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#else
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#define ARM64_MEMSTART_SHIFT PMD_SHIFT
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#endif
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/*
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* sparsemem vmemmap imposes an additional requirement on the alignment of
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* memstart_addr, due to the fact that the base of the vmemmap region
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* has a direct correspondence, and needs to appear sufficiently aligned
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* in the virtual address space.
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*/
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#if defined(CONFIG_SPARSEMEM_VMEMMAP) && ARM64_MEMSTART_SHIFT < SECTION_SIZE_BITS
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#define ARM64_MEMSTART_ALIGN (1UL << SECTION_SIZE_BITS)
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#else
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#define ARM64_MEMSTART_ALIGN (1UL << ARM64_MEMSTART_SHIFT)
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#endif
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#endif /* __ASM_KERNEL_PGTABLE_H */
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