forked from Minki/linux
08b93ec126
R-Car M1 has many clocks, and it is possible to read/use clock ratio of these clocks from FRQMRx. But, these ratio are fixed value and these are decided by MD pin status. This patch reads MD pin status, and used fixed ratio clock for other clocks. It was tesed on bock-w board. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
231 lines
7.2 KiB
C
231 lines
7.2 KiB
C
/*
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* r8a7778 clock framework support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* based on r8a7779
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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* Copyright (C) 2011 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* MD MD MD MD PLLA PLLB EXTAL clki clkz
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* 19 18 12 11 (HMz) (MHz) (MHz)
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*----------------------------------------------------------------------------
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* 1 0 0 0 x21 x21 38.00 800 800
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* 1 0 0 1 x24 x24 33.33 800 800
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* 1 0 1 0 x28 x28 28.50 800 800
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* 1 0 1 1 x32 x32 25.00 800 800
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* 1 1 0 1 x24 x21 33.33 800 700
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* 1 1 1 0 x28 x21 28.50 800 600
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* 1 1 1 1 x32 x24 25.00 800 600
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*/
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#include <linux/io.h>
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#include <linux/sh_clk.h>
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#include <linux/clkdev.h>
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#include <mach/clock.h>
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#include <mach/common.h>
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#define MSTPCR0 IOMEM(0xffc80030)
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#define MSTPCR1 IOMEM(0xffc80034)
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#define MSTPCR3 IOMEM(0xffc8003c)
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#define MSTPSR1 IOMEM(0xffc80044)
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#define MSTPSR4 IOMEM(0xffc80048)
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#define MSTPSR6 IOMEM(0xffc8004c)
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#define MSTPCR4 IOMEM(0xffc80050)
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#define MSTPCR5 IOMEM(0xffc80054)
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#define MSTPCR6 IOMEM(0xffc80058)
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#define MODEMR 0xFFCC0020
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#define MD(nr) BIT(nr)
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/* ioremap() through clock mapping mandatory to avoid
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* collision with ARM coherent DMA virtual memory range.
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*/
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static struct clk_mapping cpg_mapping = {
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.phys = 0xffc80000,
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.len = 0x80,
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};
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static struct clk extal_clk = {
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/* .rate will be updated on r8a7778_clock_init() */
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.mapping = &cpg_mapping,
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};
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/*
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* clock ratio of these clock will be updated
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* on r8a7778_clock_init()
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*/
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SH_FIXED_RATIO_CLK_SET(plla_clk, extal_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(pllb_clk, extal_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(i_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(s_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(s1_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(s3_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(s4_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(b_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(out_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(p_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(g_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(z_clk, pllb_clk, 1, 1);
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static struct clk *main_clks[] = {
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&extal_clk,
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&plla_clk,
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&pllb_clk,
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&i_clk,
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&s_clk,
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&s1_clk,
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&s3_clk,
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&s4_clk,
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&b_clk,
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&out_clk,
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&p_clk,
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&g_clk,
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&z_clk,
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};
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enum {
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MSTP114,
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MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
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MSTP016, MSTP015,
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MSTP_NR };
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
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[MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */
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[MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */
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[MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */
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[MSTP023] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 23, 0), /* SCIF3 */
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[MSTP022] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 22, 0), /* SCIF4 */
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[MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */
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[MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */
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[MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */
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};
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static struct clk_lookup lookups[] = {
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/* MSTP32 clocks */
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CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
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CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
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CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
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CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
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CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
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CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
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CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
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CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
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CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */
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};
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void __init r8a7778_clock_init(void)
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{
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void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
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u32 mode;
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int k, ret = 0;
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BUG_ON(!modemr);
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mode = ioread32(modemr);
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iounmap(modemr);
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switch (mode & (MD(19) | MD(18) | MD(12) | MD(11))) {
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case MD(19):
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extal_clk.rate = 38000000;
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SH_CLK_SET_RATIO(&plla_clk_ratio, 21, 1);
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SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1);
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break;
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case MD(19) | MD(11):
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extal_clk.rate = 33333333;
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SH_CLK_SET_RATIO(&plla_clk_ratio, 24, 1);
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SH_CLK_SET_RATIO(&pllb_clk_ratio, 24, 1);
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break;
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case MD(19) | MD(12):
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extal_clk.rate = 28500000;
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SH_CLK_SET_RATIO(&plla_clk_ratio, 28, 1);
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SH_CLK_SET_RATIO(&pllb_clk_ratio, 28, 1);
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break;
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case MD(19) | MD(12) | MD(11):
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extal_clk.rate = 25000000;
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SH_CLK_SET_RATIO(&plla_clk_ratio, 32, 1);
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SH_CLK_SET_RATIO(&pllb_clk_ratio, 32, 1);
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break;
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case MD(19) | MD(18) | MD(11):
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extal_clk.rate = 33333333;
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SH_CLK_SET_RATIO(&plla_clk_ratio, 24, 1);
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SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1);
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break;
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case MD(19) | MD(18) | MD(12):
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extal_clk.rate = 28500000;
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SH_CLK_SET_RATIO(&plla_clk_ratio, 28, 1);
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SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1);
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break;
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case MD(19) | MD(18) | MD(12) | MD(11):
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extal_clk.rate = 25000000;
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SH_CLK_SET_RATIO(&plla_clk_ratio, 32, 1);
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SH_CLK_SET_RATIO(&pllb_clk_ratio, 24, 1);
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break;
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default:
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BUG();
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}
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if (mode & MD(1)) {
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SH_CLK_SET_RATIO(&i_clk_ratio, 1, 1);
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SH_CLK_SET_RATIO(&s_clk_ratio, 1, 3);
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SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 6);
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SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
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SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
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SH_CLK_SET_RATIO(&p_clk_ratio, 1, 12);
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SH_CLK_SET_RATIO(&g_clk_ratio, 1, 12);
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if (mode & MD(2)) {
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SH_CLK_SET_RATIO(&b_clk_ratio, 1, 18);
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SH_CLK_SET_RATIO(&out_clk_ratio, 1, 18);
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} else {
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SH_CLK_SET_RATIO(&b_clk_ratio, 1, 12);
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SH_CLK_SET_RATIO(&out_clk_ratio, 1, 12);
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}
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} else {
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SH_CLK_SET_RATIO(&i_clk_ratio, 1, 1);
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SH_CLK_SET_RATIO(&s_clk_ratio, 1, 4);
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SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 8);
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SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
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SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
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SH_CLK_SET_RATIO(&p_clk_ratio, 1, 16);
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SH_CLK_SET_RATIO(&g_clk_ratio, 1, 12);
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if (mode & MD(2)) {
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SH_CLK_SET_RATIO(&b_clk_ratio, 1, 16);
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SH_CLK_SET_RATIO(&out_clk_ratio, 1, 16);
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} else {
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SH_CLK_SET_RATIO(&b_clk_ratio, 1, 12);
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SH_CLK_SET_RATIO(&out_clk_ratio, 1, 12);
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}
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}
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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ret = clk_register(main_clks[k]);
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if (!ret)
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ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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if (!ret)
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shmobile_clk_init();
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else
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panic("failed to setup r8a7778 clocks\n");
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}
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