forked from Minki/linux
f5f7eac41d
Pass the original flags to rwlock arch-code, so that it can re-enable interrupts if implemented for that architecture. Initially, make __raw_read_lock_flags and __raw_write_lock_flags stubs which just do the same thing as non-flags variants. Signed-off-by: Petr Tesarik <ptesarik@suse.cz> Signed-off-by: Robin Holt <holt@sgi.com> Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: <linux-arch@vger.kernel.org> Acked-by: Ingo Molnar <mingo@elte.hu> Cc: "Luck, Tony" <tony.luck@intel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
177 lines
3.3 KiB
C
177 lines
3.3 KiB
C
#ifndef _ALPHA_SPINLOCK_H
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#define _ALPHA_SPINLOCK_H
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#include <asm/system.h>
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#include <linux/kernel.h>
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#include <asm/current.h>
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/*
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* Simple spin lock operations. There are two variants, one clears IRQ's
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* on the local processor, one does not.
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*
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* We make no fairness assumptions. They have a cost.
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*/
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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#define __raw_spin_is_locked(x) ((x)->lock != 0)
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#define __raw_spin_unlock_wait(x) \
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do { cpu_relax(); } while ((x)->lock)
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static inline void __raw_spin_unlock(raw_spinlock_t * lock)
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{
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mb();
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lock->lock = 0;
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}
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static inline void __raw_spin_lock(raw_spinlock_t * lock)
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{
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long tmp;
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__asm__ __volatile__(
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"1: ldl_l %0,%1\n"
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" bne %0,2f\n"
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" lda %0,1\n"
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" stl_c %0,%1\n"
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" beq %0,2f\n"
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" mb\n"
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".subsection 2\n"
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"2: ldl %0,%1\n"
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" bne %0,2b\n"
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" br 1b\n"
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".previous"
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: "=&r" (tmp), "=m" (lock->lock)
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: "m"(lock->lock) : "memory");
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}
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static inline int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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return !test_and_set_bit(0, &lock->lock);
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}
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/***********************************************************/
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static inline int __raw_read_can_lock(raw_rwlock_t *lock)
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{
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return (lock->lock & 1) == 0;
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}
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static inline int __raw_write_can_lock(raw_rwlock_t *lock)
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{
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return lock->lock == 0;
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}
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static inline void __raw_read_lock(raw_rwlock_t *lock)
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{
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long regx;
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__asm__ __volatile__(
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"1: ldl_l %1,%0\n"
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" blbs %1,6f\n"
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" subl %1,2,%1\n"
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" stl_c %1,%0\n"
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" beq %1,6f\n"
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" mb\n"
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".subsection 2\n"
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"6: ldl %1,%0\n"
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" blbs %1,6b\n"
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" br 1b\n"
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".previous"
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: "=m" (*lock), "=&r" (regx)
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: "m" (*lock) : "memory");
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}
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static inline void __raw_write_lock(raw_rwlock_t *lock)
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{
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long regx;
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__asm__ __volatile__(
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"1: ldl_l %1,%0\n"
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" bne %1,6f\n"
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" lda %1,1\n"
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" stl_c %1,%0\n"
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" beq %1,6f\n"
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" mb\n"
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".subsection 2\n"
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"6: ldl %1,%0\n"
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" bne %1,6b\n"
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" br 1b\n"
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".previous"
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: "=m" (*lock), "=&r" (regx)
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: "m" (*lock) : "memory");
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}
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static inline int __raw_read_trylock(raw_rwlock_t * lock)
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{
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long regx;
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int success;
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__asm__ __volatile__(
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"1: ldl_l %1,%0\n"
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" lda %2,0\n"
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" blbs %1,2f\n"
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" subl %1,2,%2\n"
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" stl_c %2,%0\n"
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" beq %2,6f\n"
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"2: mb\n"
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".subsection 2\n"
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"6: br 1b\n"
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".previous"
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: "=m" (*lock), "=&r" (regx), "=&r" (success)
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: "m" (*lock) : "memory");
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return success;
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}
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static inline int __raw_write_trylock(raw_rwlock_t * lock)
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{
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long regx;
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int success;
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__asm__ __volatile__(
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"1: ldl_l %1,%0\n"
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" lda %2,0\n"
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" bne %1,2f\n"
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" lda %2,1\n"
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" stl_c %2,%0\n"
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" beq %2,6f\n"
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"2: mb\n"
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".subsection 2\n"
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"6: br 1b\n"
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".previous"
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: "=m" (*lock), "=&r" (regx), "=&r" (success)
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: "m" (*lock) : "memory");
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return success;
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}
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static inline void __raw_read_unlock(raw_rwlock_t * lock)
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{
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long regx;
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__asm__ __volatile__(
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" mb\n"
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"1: ldl_l %1,%0\n"
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" addl %1,2,%1\n"
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" stl_c %1,%0\n"
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" beq %1,6f\n"
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".subsection 2\n"
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"6: br 1b\n"
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".previous"
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: "=m" (*lock), "=&r" (regx)
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: "m" (*lock) : "memory");
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}
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static inline void __raw_write_unlock(raw_rwlock_t * lock)
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{
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mb();
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lock->lock = 0;
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}
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#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock)
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#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock)
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#define _raw_spin_relax(lock) cpu_relax()
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#define _raw_read_relax(lock) cpu_relax()
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#define _raw_write_relax(lock) cpu_relax()
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#endif /* _ALPHA_SPINLOCK_H */
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