baf94e6ebf
In the lastest SoC, M4U has its special power domain. thus, If the engine begin to work, it should help enable the power for M4U firstly. Currently if the engine work, it always enable the power/clocks for smi-larbs/smi-common. This patch adds device_link for smi-common and M4U. then, if smi-common power is enabled, the M4U power also is powered on automatically. Normally M4U connect with several smi-larbs and their smi-common always are the same, In this patch it get smi-common dev from the last smi-larb device, then add the device_link. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Tomasz Figa <tfiga@chromium.org> Link: https://lore.kernel.org/r/20210111111914.22211-19-yong.wu@mediatek.com Signed-off-by: Will Deacon <will@kernel.org>
104 lines
2.2 KiB
C
104 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2016 MediaTek Inc.
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* Author: Honghui Zhang <honghui.zhang@mediatek.com>
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*/
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#ifndef _MTK_IOMMU_H_
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#define _MTK_IOMMU_H_
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/io-pgtable.h>
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#include <linux/iommu.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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#include <linux/dma-mapping.h>
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#include <soc/mediatek/smi.h>
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#include <dt-bindings/memory/mtk-memory-port.h>
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#define MTK_LARB_COM_MAX 8
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#define MTK_LARB_SUBCOM_MAX 4
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struct mtk_iommu_suspend_reg {
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union {
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u32 standard_axi_mode;/* v1 */
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u32 misc_ctrl;/* v2 */
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};
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u32 dcm_dis;
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u32 ctrl_reg;
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u32 int_control0;
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u32 int_main_control;
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u32 ivrp_paddr;
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u32 vld_pa_rng;
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u32 wr_len_ctrl;
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};
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enum mtk_iommu_plat {
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M4U_MT2701,
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M4U_MT2712,
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M4U_MT6779,
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M4U_MT8167,
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M4U_MT8173,
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M4U_MT8183,
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};
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struct mtk_iommu_plat_data {
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enum mtk_iommu_plat m4u_plat;
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u32 flags;
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u32 inv_sel_reg;
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unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
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};
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struct mtk_iommu_domain;
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struct mtk_iommu_data {
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void __iomem *base;
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int irq;
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struct device *dev;
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struct clk *bclk;
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phys_addr_t protect_base; /* protect memory base */
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struct mtk_iommu_suspend_reg reg;
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struct mtk_iommu_domain *m4u_dom;
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struct iommu_group *m4u_group;
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bool enable_4GB;
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spinlock_t tlb_lock; /* lock for tlb range flush */
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struct iommu_device iommu;
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const struct mtk_iommu_plat_data *plat_data;
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struct device *smicomm_dev;
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struct dma_iommu_mapping *mapping; /* For mtk_iommu_v1.c */
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struct list_head list;
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struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
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};
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static inline int compare_of(struct device *dev, void *data)
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{
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return dev->of_node == data;
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}
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static inline void release_of(struct device *dev, void *data)
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{
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of_node_put(data);
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}
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static inline int mtk_iommu_bind(struct device *dev)
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{
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struct mtk_iommu_data *data = dev_get_drvdata(dev);
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return component_bind_all(dev, &data->larb_imu);
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}
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static inline void mtk_iommu_unbind(struct device *dev)
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{
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struct mtk_iommu_data *data = dev_get_drvdata(dev);
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component_unbind_all(dev, &data->larb_imu);
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}
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#endif
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