Ville Syrjälä 0846697c67 drm/i915/chv: Implement WaDisableCSUnitClockGating:chv ... This workaround is listed for CHV, but not for BDW. However BSpec notes that on BDW CSunit clock gating is always disabled irrespective of the relevant bit in the GEN6_UGCTL1 registers. For CHV however, such text is not present in BSpec, so it seems safer to just set the bit. Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2014-05-20 15:19:39 +02:00
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drm	drm/i915/chv: Implement WaDisableCSUnitClockGating:chv	2014-05-20 15:19:39 +02:00
host1x	gpu: host1x: handle the correct # of syncpt regs	2014-04-16 17:11:04 +02:00
vga
Makefile