forked from Minki/linux
6f2bcceb27
Yet other direct usages of the pipe number instead of pipe_name(). We've been tracking them lately but managed to miss these last ones. v2: Catch them all! (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
621 lines
18 KiB
C
621 lines
18 KiB
C
/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Author: Jani Nikula <jani.nikula@intel.com>
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*/
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_edid.h>
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#include <drm/i915_drm.h>
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#include <linux/slab.h>
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#include "i915_drv.h"
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#include "intel_drv.h"
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#include "intel_dsi.h"
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#include "intel_dsi_cmd.h"
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/* the sub-encoders aka panel drivers */
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static const struct intel_dsi_device intel_dsi_devices[] = {
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};
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static void vlv_cck_modify(struct drm_i915_private *dev_priv, u32 reg, u32 val,
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u32 mask)
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{
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u32 tmp = vlv_cck_read(dev_priv, reg);
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tmp &= ~mask;
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tmp |= val;
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vlv_cck_write(dev_priv, reg, tmp);
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}
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static void band_gap_wa(struct drm_i915_private *dev_priv)
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{
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mutex_lock(&dev_priv->dpio_lock);
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/* Enable bandgap fix in GOP driver */
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vlv_cck_modify(dev_priv, 0x6D, 0x00010000, 0x00030000);
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msleep(20);
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vlv_cck_modify(dev_priv, 0x6E, 0x00010000, 0x00030000);
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msleep(20);
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vlv_cck_modify(dev_priv, 0x6F, 0x00010000, 0x00030000);
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msleep(20);
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vlv_cck_modify(dev_priv, 0x00, 0x00008000, 0x00008000);
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msleep(20);
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vlv_cck_modify(dev_priv, 0x00, 0x00000000, 0x00008000);
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msleep(20);
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/* Turn Display Trunk on */
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vlv_cck_modify(dev_priv, 0x6B, 0x00020000, 0x00030000);
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msleep(20);
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vlv_cck_modify(dev_priv, 0x6C, 0x00020000, 0x00030000);
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msleep(20);
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vlv_cck_modify(dev_priv, 0x6D, 0x00020000, 0x00030000);
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msleep(20);
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vlv_cck_modify(dev_priv, 0x6E, 0x00020000, 0x00030000);
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msleep(20);
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vlv_cck_modify(dev_priv, 0x6F, 0x00020000, 0x00030000);
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mutex_unlock(&dev_priv->dpio_lock);
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/* Need huge delay, otherwise clock is not stable */
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msleep(100);
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}
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static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
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{
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return container_of(intel_attached_encoder(connector),
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struct intel_dsi, base);
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}
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static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
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{
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return intel_dsi->dev.type == INTEL_DSI_VIDEO_MODE;
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}
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static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
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{
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return intel_dsi->dev.type == INTEL_DSI_COMMAND_MODE;
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}
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static void intel_dsi_hot_plug(struct intel_encoder *encoder)
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{
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DRM_DEBUG_KMS("\n");
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}
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static bool intel_dsi_compute_config(struct intel_encoder *encoder,
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struct intel_crtc_config *config)
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{
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struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
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base);
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struct intel_connector *intel_connector = intel_dsi->attached_connector;
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struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
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struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
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struct drm_display_mode *mode = &config->requested_mode;
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DRM_DEBUG_KMS("\n");
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if (fixed_mode)
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intel_fixed_panel_mode(fixed_mode, adjusted_mode);
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if (intel_dsi->dev.dev_ops->mode_fixup)
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return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev,
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mode, adjusted_mode);
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return true;
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}
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static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
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{
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DRM_DEBUG_KMS("\n");
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vlv_enable_dsi_pll(encoder);
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}
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static void intel_dsi_pre_enable(struct intel_encoder *encoder)
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{
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DRM_DEBUG_KMS("\n");
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}
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static void intel_dsi_enable(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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int pipe = intel_crtc->pipe;
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u32 temp;
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DRM_DEBUG_KMS("\n");
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temp = I915_READ(MIPI_DEVICE_READY(pipe));
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if ((temp & DEVICE_READY) == 0) {
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temp &= ~ULPS_STATE_MASK;
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I915_WRITE(MIPI_DEVICE_READY(pipe), temp | DEVICE_READY);
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} else if (temp & ULPS_STATE_MASK) {
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temp &= ~ULPS_STATE_MASK;
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I915_WRITE(MIPI_DEVICE_READY(pipe), temp | ULPS_STATE_EXIT);
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/*
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* We need to ensure that there is a minimum of 1 ms time
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* available before clearing the UPLS exit state.
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*/
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msleep(2);
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I915_WRITE(MIPI_DEVICE_READY(pipe), temp);
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}
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if (is_cmd_mode(intel_dsi))
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I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
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if (is_vid_mode(intel_dsi)) {
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msleep(20); /* XXX */
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dpi_send_cmd(intel_dsi, TURN_ON);
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msleep(100);
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/* assert ip_tg_enable signal */
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temp = I915_READ(MIPI_PORT_CTRL(pipe));
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I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
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POSTING_READ(MIPI_PORT_CTRL(pipe));
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}
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intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
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}
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static void intel_dsi_disable(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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int pipe = intel_crtc->pipe;
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u32 temp;
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DRM_DEBUG_KMS("\n");
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intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
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if (is_vid_mode(intel_dsi)) {
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dpi_send_cmd(intel_dsi, SHUTDOWN);
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msleep(10);
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/* de-assert ip_tg_enable signal */
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temp = I915_READ(MIPI_PORT_CTRL(pipe));
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I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
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POSTING_READ(MIPI_PORT_CTRL(pipe));
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msleep(2);
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}
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temp = I915_READ(MIPI_DEVICE_READY(pipe));
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if (temp & DEVICE_READY) {
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temp &= ~DEVICE_READY;
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temp &= ~ULPS_STATE_MASK;
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I915_WRITE(MIPI_DEVICE_READY(pipe), temp);
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}
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}
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static void intel_dsi_post_disable(struct intel_encoder *encoder)
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{
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DRM_DEBUG_KMS("\n");
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vlv_disable_dsi_pll(encoder);
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}
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static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
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enum pipe *pipe)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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u32 port, func;
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enum pipe p;
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DRM_DEBUG_KMS("\n");
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/* XXX: this only works for one DSI output */
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for (p = PIPE_A; p <= PIPE_B; p++) {
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port = I915_READ(MIPI_PORT_CTRL(p));
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func = I915_READ(MIPI_DSI_FUNC_PRG(p));
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if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
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if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) {
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*pipe = p;
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return true;
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}
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}
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}
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return false;
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}
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static void intel_dsi_get_config(struct intel_encoder *encoder,
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struct intel_crtc_config *pipe_config)
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{
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DRM_DEBUG_KMS("\n");
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/* XXX: read flags, set to adjusted_mode */
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}
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static int intel_dsi_mode_valid(struct drm_connector *connector,
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struct drm_display_mode *mode)
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{
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struct intel_connector *intel_connector = to_intel_connector(connector);
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struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
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struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
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DRM_DEBUG_KMS("\n");
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if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
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DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
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return MODE_NO_DBLESCAN;
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}
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if (fixed_mode) {
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if (mode->hdisplay > fixed_mode->hdisplay)
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return MODE_PANEL;
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if (mode->vdisplay > fixed_mode->vdisplay)
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return MODE_PANEL;
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}
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return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode);
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}
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/* return txclkesc cycles in terms of divider and duration in us */
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static u16 txclkesc(u32 divider, unsigned int us)
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{
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switch (divider) {
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case ESCAPE_CLOCK_DIVIDER_1:
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default:
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return 20 * us;
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case ESCAPE_CLOCK_DIVIDER_2:
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return 10 * us;
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case ESCAPE_CLOCK_DIVIDER_4:
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return 5 * us;
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}
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}
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/* return pixels in terms of txbyteclkhs */
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static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count)
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{
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return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count);
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}
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static void set_dsi_timings(struct drm_encoder *encoder,
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const struct drm_display_mode *mode)
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{
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
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int pipe = intel_crtc->pipe;
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unsigned int bpp = intel_crtc->config.pipe_bpp;
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unsigned int lane_count = intel_dsi->lane_count;
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u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
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hactive = mode->hdisplay;
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hfp = mode->hsync_start - mode->hdisplay;
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hsync = mode->hsync_end - mode->hsync_start;
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hbp = mode->htotal - mode->hsync_end;
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vfp = mode->vsync_start - mode->vdisplay;
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vsync = mode->vsync_end - mode->vsync_start;
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vbp = mode->vtotal - mode->vsync_end;
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/* horizontal values are in terms of high speed byte clock */
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hactive = txbyteclkhs(hactive, bpp, lane_count);
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hfp = txbyteclkhs(hfp, bpp, lane_count);
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hsync = txbyteclkhs(hsync, bpp, lane_count);
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hbp = txbyteclkhs(hbp, bpp, lane_count);
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I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
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I915_WRITE(MIPI_HFP_COUNT(pipe), hfp);
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/* meaningful for video mode non-burst sync pulse mode only, can be zero
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* for non-burst sync events and burst modes */
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I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync);
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I915_WRITE(MIPI_HBP_COUNT(pipe), hbp);
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/* vertical values are in terms of lines */
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I915_WRITE(MIPI_VFP_COUNT(pipe), vfp);
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I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync);
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I915_WRITE(MIPI_VBP_COUNT(pipe), vbp);
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}
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static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
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{
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struct drm_encoder *encoder = &intel_encoder->base;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
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struct drm_display_mode *adjusted_mode =
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&intel_crtc->config.adjusted_mode;
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int pipe = intel_crtc->pipe;
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unsigned int bpp = intel_crtc->config.pipe_bpp;
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u32 val, tmp;
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DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
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/* Update the DSI PLL */
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vlv_enable_dsi_pll(intel_encoder);
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/* XXX: Location of the call */
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band_gap_wa(dev_priv);
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/* escape clock divider, 20MHz, shared for A and C. device ready must be
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* off when doing this! txclkesc? */
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tmp = I915_READ(MIPI_CTRL(0));
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tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
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I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1);
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/* read request priority is per pipe */
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tmp = I915_READ(MIPI_CTRL(pipe));
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tmp &= ~READ_REQUEST_PRIORITY_MASK;
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I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH);
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/* XXX: why here, why like this? handling in irq handler?! */
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I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff);
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I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff);
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I915_WRITE(MIPI_DPHY_PARAM(pipe),
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0x3c << EXIT_ZERO_COUNT_SHIFT |
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0x1f << TRAIL_COUNT_SHIFT |
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0xc5 << CLK_ZERO_COUNT_SHIFT |
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0x1f << PREPARE_COUNT_SHIFT);
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I915_WRITE(MIPI_DPI_RESOLUTION(pipe),
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adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
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adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
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set_dsi_timings(encoder, adjusted_mode);
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val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
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if (is_cmd_mode(intel_dsi)) {
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val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
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val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
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} else {
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val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
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/* XXX: cross-check bpp vs. pixel format? */
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val |= intel_dsi->pixel_format;
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}
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I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val);
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/* timeouts for recovery. one frame IIUC. if counter expires, EOT and
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* stop state. */
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/*
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* In burst mode, value greater than one DPI line Time in byte clock
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* (txbyteclkhs) To timeout this timer 1+ of the above said value is
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* recommended.
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*
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* In non-burst mode, Value greater than one DPI frame time in byte
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* clock(txbyteclkhs) To timeout this timer 1+ of the above said value
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* is recommended.
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*
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* In DBI only mode, value greater than one DBI frame time in byte
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* clock(txbyteclkhs) To timeout this timer 1+ of the above said value
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* is recommended.
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*/
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if (is_vid_mode(intel_dsi) &&
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intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
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I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
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txbyteclkhs(adjusted_mode->htotal, bpp,
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intel_dsi->lane_count) + 1);
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} else {
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I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
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txbyteclkhs(adjusted_mode->vtotal *
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adjusted_mode->htotal,
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bpp, intel_dsi->lane_count) + 1);
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}
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I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), 8309); /* max */
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I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), 0x14); /* max */
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I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), 0xffff); /* max */
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/* dphy stuff */
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/* in terms of low power clock */
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I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(ESCAPE_CLOCK_DIVIDER_1, 100));
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/* recovery disables */
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I915_WRITE(MIPI_EOT_DISABLE(pipe), intel_dsi->eot_disable);
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/* in terms of txbyteclkhs. actual high to low switch +
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* MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
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*
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* XXX: write MIPI_STOP_STATE_STALL?
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*/
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I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), 0x46);
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/* XXX: low power clock equivalence in terms of byte clock. the number
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* of byte clocks occupied in one low power clock. based on txbyteclkhs
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* and txclkesc. txclkesc time / txbyteclk time * (105 +
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* MIPI_STOP_STATE_STALL) / 105.???
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*/
|
|
I915_WRITE(MIPI_LP_BYTECLK(pipe), 4);
|
|
|
|
/* the bw essential for transmitting 16 long packets containing 252
|
|
* bytes meant for dcs write memory command is programmed in this
|
|
* register in terms of byte clocks. based on dsi transfer rate and the
|
|
* number of lanes configured the time taken to transmit 16 long packets
|
|
* in a dsi stream varies. */
|
|
I915_WRITE(MIPI_DBI_BW_CTRL(pipe), 0x820);
|
|
|
|
I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe),
|
|
0xa << LP_HS_SSW_CNT_SHIFT |
|
|
0x14 << HS_LP_PWR_SW_CNT_SHIFT);
|
|
|
|
if (is_vid_mode(intel_dsi))
|
|
I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
|
|
intel_dsi->video_mode_format);
|
|
}
|
|
|
|
static enum drm_connector_status
|
|
intel_dsi_detect(struct drm_connector *connector, bool force)
|
|
{
|
|
struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
|
|
DRM_DEBUG_KMS("\n");
|
|
return intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
|
|
}
|
|
|
|
static int intel_dsi_get_modes(struct drm_connector *connector)
|
|
{
|
|
struct intel_connector *intel_connector = to_intel_connector(connector);
|
|
struct drm_display_mode *mode;
|
|
|
|
DRM_DEBUG_KMS("\n");
|
|
|
|
if (!intel_connector->panel.fixed_mode) {
|
|
DRM_DEBUG_KMS("no fixed mode\n");
|
|
return 0;
|
|
}
|
|
|
|
mode = drm_mode_duplicate(connector->dev,
|
|
intel_connector->panel.fixed_mode);
|
|
if (!mode) {
|
|
DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
|
|
return 0;
|
|
}
|
|
|
|
drm_mode_probed_add(connector, mode);
|
|
return 1;
|
|
}
|
|
|
|
static void intel_dsi_destroy(struct drm_connector *connector)
|
|
{
|
|
struct intel_connector *intel_connector = to_intel_connector(connector);
|
|
|
|
DRM_DEBUG_KMS("\n");
|
|
intel_panel_fini(&intel_connector->panel);
|
|
drm_connector_cleanup(connector);
|
|
kfree(connector);
|
|
}
|
|
|
|
static const struct drm_encoder_funcs intel_dsi_funcs = {
|
|
.destroy = intel_encoder_destroy,
|
|
};
|
|
|
|
static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
|
|
.get_modes = intel_dsi_get_modes,
|
|
.mode_valid = intel_dsi_mode_valid,
|
|
.best_encoder = intel_best_encoder,
|
|
};
|
|
|
|
static const struct drm_connector_funcs intel_dsi_connector_funcs = {
|
|
.dpms = intel_connector_dpms,
|
|
.detect = intel_dsi_detect,
|
|
.destroy = intel_dsi_destroy,
|
|
.fill_modes = drm_helper_probe_single_connector_modes,
|
|
};
|
|
|
|
bool intel_dsi_init(struct drm_device *dev)
|
|
{
|
|
struct intel_dsi *intel_dsi;
|
|
struct intel_encoder *intel_encoder;
|
|
struct drm_encoder *encoder;
|
|
struct intel_connector *intel_connector;
|
|
struct drm_connector *connector;
|
|
struct drm_display_mode *fixed_mode = NULL;
|
|
const struct intel_dsi_device *dsi;
|
|
unsigned int i;
|
|
|
|
DRM_DEBUG_KMS("\n");
|
|
|
|
intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
|
|
if (!intel_dsi)
|
|
return false;
|
|
|
|
intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
|
|
if (!intel_connector) {
|
|
kfree(intel_dsi);
|
|
return false;
|
|
}
|
|
|
|
intel_encoder = &intel_dsi->base;
|
|
encoder = &intel_encoder->base;
|
|
intel_dsi->attached_connector = intel_connector;
|
|
|
|
connector = &intel_connector->base;
|
|
|
|
drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
|
|
|
|
/* XXX: very likely not all of these are needed */
|
|
intel_encoder->hot_plug = intel_dsi_hot_plug;
|
|
intel_encoder->compute_config = intel_dsi_compute_config;
|
|
intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
|
|
intel_encoder->pre_enable = intel_dsi_pre_enable;
|
|
intel_encoder->enable = intel_dsi_enable;
|
|
intel_encoder->mode_set = intel_dsi_mode_set;
|
|
intel_encoder->disable = intel_dsi_disable;
|
|
intel_encoder->post_disable = intel_dsi_post_disable;
|
|
intel_encoder->get_hw_state = intel_dsi_get_hw_state;
|
|
intel_encoder->get_config = intel_dsi_get_config;
|
|
|
|
intel_connector->get_hw_state = intel_connector_get_hw_state;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) {
|
|
dsi = &intel_dsi_devices[i];
|
|
intel_dsi->dev = *dsi;
|
|
|
|
if (dsi->dev_ops->init(&intel_dsi->dev))
|
|
break;
|
|
}
|
|
|
|
if (i == ARRAY_SIZE(intel_dsi_devices)) {
|
|
DRM_DEBUG_KMS("no device found\n");
|
|
goto err;
|
|
}
|
|
|
|
intel_encoder->type = INTEL_OUTPUT_DSI;
|
|
intel_encoder->crtc_mask = (1 << 0); /* XXX */
|
|
|
|
intel_encoder->cloneable = false;
|
|
drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
|
|
DRM_MODE_CONNECTOR_DSI);
|
|
|
|
drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
|
|
|
|
connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
|
|
connector->interlace_allowed = false;
|
|
connector->doublescan_allowed = false;
|
|
|
|
intel_connector_attach_encoder(intel_connector, intel_encoder);
|
|
|
|
drm_sysfs_connector_add(connector);
|
|
|
|
fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev);
|
|
if (!fixed_mode) {
|
|
DRM_DEBUG_KMS("no fixed mode\n");
|
|
goto err;
|
|
}
|
|
|
|
fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
|
|
intel_panel_init(&intel_connector->panel, fixed_mode);
|
|
|
|
return true;
|
|
|
|
err:
|
|
drm_encoder_cleanup(&intel_encoder->base);
|
|
kfree(intel_dsi);
|
|
kfree(intel_connector);
|
|
|
|
return false;
|
|
}
|