forked from Minki/linux
a31e58e129
Some of the APIC incarnations are operating in lowest priority delivery
mode. This worked as long as the vector management code allocated the same
vector on all possible CPUs for each interrupt.
Lowest priority delivery mode does not necessarily respect the affinity
setting and may redirect to some other online CPU. This was documented
somewhere in the old code and the conversion to single target delivery
missed to update the delivery mode of the affected APIC drivers which
results in spurious interrupts on some of the affected CPU/Chipset
combinations.
Switch the APIC drivers over to Fixed delivery mode and remove all
leftovers of lowest priority delivery mode.
Switching to Fixed delivery mode is not a problem on these CPUs because the
kernel already uses Fixed delivery mode for IPIs. The reason for this is
that th SDM explicitely forbids lowest prio mode for IPIs. The reason is
obvious: If the irq routing does not honor destination targets in lowest
prio mode then an IPI targeted at CPU1 might end up on CPU0, which would be
a fatal problem in many cases.
As a consequence of this change, the apic::irq_delivery_mode field is now
pointless, but this needs to be cleaned up in a separate patch.
Fixes: fdba46ffb4
("x86/apic: Get rid of multi CPU affinity")
Reported-by: vcaputo@pengaru.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: vcaputo@pengaru.com
Cc: Pavel Machek <pavel@ucw.cz>
Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1712281140440.1688@nanos
250 lines
5.8 KiB
C
250 lines
5.8 KiB
C
/*
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* Default generic APIC driver. This handles up to 8 CPUs.
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*
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* Copyright 2003 Andi Kleen, SuSE Labs.
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* Subject to the GNU Public License, v.2
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*
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* Generic x86 APIC driver probe layer.
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*/
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#include <linux/threads.h>
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#include <linux/cpumask.h>
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#include <linux/export.h>
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/ctype.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <asm/fixmap.h>
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#include <asm/mpspec.h>
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#include <asm/apicdef.h>
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#include <asm/apic.h>
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#include <asm/setup.h>
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#include <linux/smp.h>
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#include <asm/ipi.h>
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#include <linux/interrupt.h>
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#include <asm/acpi.h>
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#include <asm/e820/api.h>
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#ifdef CONFIG_HOTPLUG_CPU
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#define DEFAULT_SEND_IPI (1)
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#else
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#define DEFAULT_SEND_IPI (0)
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#endif
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int no_broadcast = DEFAULT_SEND_IPI;
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static __init int no_ipi_broadcast(char *str)
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{
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get_option(&str, &no_broadcast);
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pr_info("Using %s mode\n",
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no_broadcast ? "No IPI Broadcast" : "IPI Broadcast");
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return 1;
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}
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__setup("no_ipi_broadcast=", no_ipi_broadcast);
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static int __init print_ipi_mode(void)
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{
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pr_info("Using IPI %s mode\n",
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no_broadcast ? "No-Shortcut" : "Shortcut");
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return 0;
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}
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late_initcall(print_ipi_mode);
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static int default_x86_32_early_logical_apicid(int cpu)
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{
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return 1 << cpu;
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}
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static void setup_apic_flat_routing(void)
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{
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#ifdef CONFIG_X86_IO_APIC
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printk(KERN_INFO
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"Enabling APIC mode: Flat. Using %d I/O APICs\n",
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nr_ioapics);
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#endif
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}
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static int default_apic_id_registered(void)
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{
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return physid_isset(read_apic_id(), phys_cpu_present_map);
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}
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/*
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* Set up the logical destination ID. Intel recommends to set DFR, LDR and
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* TPR before enabling an APIC. See e.g. "AP-388 82489DX User's Manual"
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* (Intel document number 292116).
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*/
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static void default_init_apic_ldr(void)
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{
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unsigned long val;
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apic_write(APIC_DFR, APIC_DFR_VALUE);
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val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
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val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
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apic_write(APIC_LDR, val);
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}
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static int default_phys_pkg_id(int cpuid_apic, int index_msb)
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{
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return cpuid_apic >> index_msb;
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}
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/* should be called last. */
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static int probe_default(void)
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{
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return 1;
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}
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static struct apic apic_default __ro_after_init = {
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.name = "default",
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.probe = probe_default,
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.acpi_madt_oem_check = NULL,
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.apic_id_valid = default_apic_id_valid,
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.apic_id_registered = default_apic_id_registered,
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.irq_delivery_mode = dest_Fixed,
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/* logical delivery broadcast to all CPUs: */
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.irq_dest_mode = 1,
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.disable_esr = 0,
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.dest_logical = APIC_DEST_LOGICAL,
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.check_apicid_used = default_check_apicid_used,
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.init_apic_ldr = default_init_apic_ldr,
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.ioapic_phys_id_map = default_ioapic_phys_id_map,
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.setup_apic_routing = setup_apic_flat_routing,
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.cpu_present_to_apicid = default_cpu_present_to_apicid,
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.apicid_to_cpu_present = physid_set_mask_of_physid,
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.check_phys_apicid_present = default_check_phys_apicid_present,
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.phys_pkg_id = default_phys_pkg_id,
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.get_apic_id = default_get_apic_id,
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.set_apic_id = NULL,
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.calc_dest_apicid = apic_flat_calc_apicid,
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.send_IPI = default_send_IPI_single,
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.send_IPI_mask = default_send_IPI_mask_logical,
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.send_IPI_mask_allbutself = default_send_IPI_mask_allbutself_logical,
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.send_IPI_allbutself = default_send_IPI_allbutself,
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.send_IPI_all = default_send_IPI_all,
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.send_IPI_self = default_send_IPI_self,
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.inquire_remote_apic = default_inquire_remote_apic,
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.read = native_apic_mem_read,
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.write = native_apic_mem_write,
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.eoi_write = native_apic_mem_write,
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.icr_read = native_apic_icr_read,
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.icr_write = native_apic_icr_write,
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.wait_icr_idle = native_apic_wait_icr_idle,
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.safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
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.x86_32_early_logical_apicid = default_x86_32_early_logical_apicid,
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};
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apic_driver(apic_default);
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struct apic *apic __ro_after_init = &apic_default;
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EXPORT_SYMBOL_GPL(apic);
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static int cmdline_apic __initdata;
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static int __init parse_apic(char *arg)
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{
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struct apic **drv;
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if (!arg)
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return -EINVAL;
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for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
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if (!strcmp((*drv)->name, arg)) {
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apic = *drv;
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cmdline_apic = 1;
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return 0;
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}
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}
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/* Parsed again by __setup for debug/verbose */
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return 0;
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}
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early_param("apic", parse_apic);
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void __init default_setup_apic_routing(void)
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{
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int version = boot_cpu_apic_version;
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if (num_possible_cpus() > 8) {
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switch (boot_cpu_data.x86_vendor) {
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case X86_VENDOR_INTEL:
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if (!APIC_XAPIC(version)) {
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def_to_bigsmp = 0;
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break;
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}
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/* If P4 and above fall through */
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case X86_VENDOR_AMD:
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def_to_bigsmp = 1;
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}
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}
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#ifdef CONFIG_X86_BIGSMP
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/*
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* This is used to switch to bigsmp mode when
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* - There is no apic= option specified by the user
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* - generic_apic_probe() has chosen apic_default as the sub_arch
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* - we find more than 8 CPUs in acpi LAPIC listing with xAPIC support
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*/
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if (!cmdline_apic && apic == &apic_default)
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generic_bigsmp_probe();
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#endif
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if (apic->setup_apic_routing)
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apic->setup_apic_routing();
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if (x86_platform.apic_post_init)
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x86_platform.apic_post_init();
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}
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void __init generic_apic_probe(void)
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{
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if (!cmdline_apic) {
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struct apic **drv;
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for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
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if ((*drv)->probe()) {
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apic = *drv;
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break;
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}
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}
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/* Not visible without early console */
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if (drv == __apicdrivers_end)
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panic("Didn't find an APIC driver");
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}
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printk(KERN_INFO "Using APIC driver %s\n", apic->name);
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}
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/* This function can switch the APIC even after the initial ->probe() */
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int __init default_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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{
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struct apic **drv;
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for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
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if (!(*drv)->acpi_madt_oem_check)
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continue;
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if (!(*drv)->acpi_madt_oem_check(oem_id, oem_table_id))
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continue;
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if (!cmdline_apic) {
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apic = *drv;
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printk(KERN_INFO "Switched to APIC driver `%s'.\n",
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apic->name);
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}
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return 1;
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}
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return 0;
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}
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