forked from Minki/linux
a9c59c2746
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
897 lines
22 KiB
C
897 lines
22 KiB
C
/*
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* File: arch/blackfin/kernel/setup.c
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* Based on:
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* Author:
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*
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* Created:
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* Description:
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*
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* Modified:
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* Copyright 2004-2006 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/delay.h>
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#include <linux/console.h>
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#include <linux/bootmem.h>
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#include <linux/seq_file.h>
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#include <linux/cpu.h>
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#include <linux/module.h>
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#include <linux/tty.h>
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#include <linux/ext2_fs.h>
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#include <linux/cramfs_fs.h>
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#include <linux/romfs_fs.h>
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#include <asm/cacheflush.h>
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#include <asm/blackfin.h>
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#include <asm/cplbinit.h>
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u16 _bfin_swrst;
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unsigned long memory_start, memory_end, physical_mem_end;
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unsigned long reserved_mem_dcache_on;
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unsigned long reserved_mem_icache_on;
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EXPORT_SYMBOL(memory_start);
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EXPORT_SYMBOL(memory_end);
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EXPORT_SYMBOL(physical_mem_end);
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EXPORT_SYMBOL(_ramend);
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#ifdef CONFIG_MTD_UCLINUX
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unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
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unsigned long _ebss;
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EXPORT_SYMBOL(memory_mtd_end);
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EXPORT_SYMBOL(memory_mtd_start);
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EXPORT_SYMBOL(mtd_size);
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#endif
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char command_line[COMMAND_LINE_SIZE];
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#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
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static void generate_cpl_tables(void);
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#endif
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void __init bf53x_cache_init(void)
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{
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#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
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generate_cpl_tables();
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#endif
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#ifdef CONFIG_BLKFIN_CACHE
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bfin_icache_init();
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printk(KERN_INFO "Instruction Cache Enabled\n");
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#endif
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#ifdef CONFIG_BLKFIN_DCACHE
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bfin_dcache_init();
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printk(KERN_INFO "Data Cache Enabled"
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# if defined CONFIG_BLKFIN_WB
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" (write-back)"
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# elif defined CONFIG_BLKFIN_WT
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" (write-through)"
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# endif
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"\n");
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#endif
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}
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void bf53x_relocate_l1_mem(void)
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{
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unsigned long l1_code_length;
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unsigned long l1_data_a_length;
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unsigned long l1_data_b_length;
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l1_code_length = _etext_l1 - _stext_l1;
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if (l1_code_length > L1_CODE_LENGTH)
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l1_code_length = L1_CODE_LENGTH;
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/* cannot complain as printk is not available as yet.
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* But we can continue booting and complain later!
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*/
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/* Copy _stext_l1 to _etext_l1 to L1 instruction SRAM */
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dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length);
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l1_data_a_length = _ebss_l1 - _sdata_l1;
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if (l1_data_a_length > L1_DATA_A_LENGTH)
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l1_data_a_length = L1_DATA_A_LENGTH;
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/* Copy _sdata_l1 to _ebss_l1 to L1 data bank A SRAM */
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dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length);
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l1_data_b_length = _ebss_b_l1 - _sdata_b_l1;
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if (l1_data_b_length > L1_DATA_B_LENGTH)
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l1_data_b_length = L1_DATA_B_LENGTH;
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/* Copy _sdata_b_l1 to _ebss_b_l1 to L1 data bank B SRAM */
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dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
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l1_data_a_length, l1_data_b_length);
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}
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/*
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* Initial parsing of the command line. Currently, we support:
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* - Controlling the linux memory size: mem=xxx[KMG]
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* - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
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* $ -> reserved memory is dcacheable
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* # -> reserved memory is icacheable
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*/
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static __init void parse_cmdline_early(char *cmdline_p)
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{
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char c = ' ', *to = cmdline_p;
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unsigned int memsize;
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for (;;) {
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if (c == ' ') {
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if (!memcmp(to, "mem=", 4)) {
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to += 4;
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memsize = memparse(to, &to);
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if (memsize)
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_ramend = memsize;
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} else if (!memcmp(to, "max_mem=", 8)) {
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to += 8;
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memsize = memparse(to, &to);
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if (memsize) {
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physical_mem_end = memsize;
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if (*to != ' ') {
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if (*to == '$'
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|| *(to + 1) == '$')
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reserved_mem_dcache_on =
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1;
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if (*to == '#'
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|| *(to + 1) == '#')
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reserved_mem_icache_on =
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1;
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}
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}
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}
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}
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c = *(to++);
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if (!c)
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break;
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}
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}
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void __init setup_arch(char **cmdline_p)
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{
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int bootmap_size;
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unsigned long l1_length, sclk, cclk;
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#ifdef CONFIG_MTD_UCLINUX
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unsigned long mtd_phys = 0;
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#endif
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#ifdef CONFIG_DUMMY_CONSOLE
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conswitchp = &dummy_con;
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#endif
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cclk = get_cclk();
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sclk = get_sclk();
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#if !defined(CONFIG_BFIN_KERNEL_CLOCK) && defined(ANOMALY_05000273)
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if (cclk == sclk)
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panic("ANOMALY 05000273, SCLK can not be same as CCLK");
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#endif
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#if defined(ANOMALY_05000266)
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bfin_read_IMDMA_D0_IRQ_STATUS();
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bfin_read_IMDMA_D1_IRQ_STATUS();
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#endif
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#ifdef DEBUG_SERIAL_EARLY_INIT
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bfin_console_init(); /* early console registration */
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/* this give a chance to get printk() working before crash. */
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#endif
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#if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
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/* we need to initialize the Flashrom device here since we might
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* do things with flash early on in the boot
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*/
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flash_probe();
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#endif
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#if defined(CONFIG_CMDLINE_BOOL)
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memset(command_line, 0, sizeof(command_line));
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strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
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command_line[sizeof(command_line) - 1] = 0;
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#endif
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/* Keep a copy of command line */
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*cmdline_p = &command_line[0];
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memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
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boot_command_line[COMMAND_LINE_SIZE - 1] = 0;
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/* setup memory defaults from the user config */
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physical_mem_end = 0;
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_ramend = CONFIG_MEM_SIZE * 1024 * 1024;
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parse_cmdline_early(&command_line[0]);
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if (physical_mem_end == 0)
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physical_mem_end = _ramend;
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/* by now the stack is part of the init task */
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memory_end = _ramend - DMA_UNCACHED_REGION;
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_ramstart = (unsigned long)__bss_stop;
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memory_start = PAGE_ALIGN(_ramstart);
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#if defined(CONFIG_MTD_UCLINUX)
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/* generic memory mapped MTD driver */
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memory_mtd_end = memory_end;
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mtd_phys = _ramstart;
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mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
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# if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
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if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
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mtd_size =
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PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
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# endif
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# if defined(CONFIG_CRAMFS)
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if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
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mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
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# endif
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# if defined(CONFIG_ROMFS_FS)
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if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
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&& ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1)
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mtd_size =
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PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
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# if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
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/* Due to a Hardware Anomaly we need to limit the size of usable
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* instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
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* 05000263 - Hardware loop corrupted when taking an ICPLB exception
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*/
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# if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
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if (memory_end >= 56 * 1024 * 1024)
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memory_end = 56 * 1024 * 1024;
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# else
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if (memory_end >= 60 * 1024 * 1024)
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memory_end = 60 * 1024 * 1024;
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# endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
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# endif /* ANOMALY_05000263 */
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# endif /* CONFIG_ROMFS_FS */
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memory_end -= mtd_size;
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if (mtd_size == 0) {
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console_init();
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panic("Don't boot kernel without rootfs attached.\n");
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}
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/* Relocate MTD image to the top of memory after the uncached memory area */
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dma_memcpy((char *)memory_end, __bss_stop, mtd_size);
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memory_mtd_start = memory_end;
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_ebss = memory_mtd_start; /* define _ebss for compatible */
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#endif /* CONFIG_MTD_UCLINUX */
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#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
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/* Due to a Hardware Anomaly we need to limit the size of usable
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* instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
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* 05000263 - Hardware loop corrupted when taking an ICPLB exception
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*/
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#if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
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if (memory_end >= 56 * 1024 * 1024)
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memory_end = 56 * 1024 * 1024;
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#else
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if (memory_end >= 60 * 1024 * 1024)
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memory_end = 60 * 1024 * 1024;
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#endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
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printk(KERN_NOTICE "Warning: limiting memory to %liMB due to hardware anomaly 05000263\n", memory_end >> 20);
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#endif /* ANOMALY_05000263 */
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#if !defined(CONFIG_MTD_UCLINUX)
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memory_end -= SIZE_4K; /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
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#endif
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init_mm.start_code = (unsigned long)_stext;
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init_mm.end_code = (unsigned long)_etext;
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init_mm.end_data = (unsigned long)_edata;
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init_mm.brk = (unsigned long)0;
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init_leds();
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printk(KERN_INFO "Blackfin support (C) 2004-2007 Analog Devices, Inc.\n");
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printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
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if (bfin_revid() != bfin_compiled_revid())
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printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
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bfin_compiled_revid(), bfin_revid());
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if (bfin_revid() < SUPPORTED_REVID)
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printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
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CPU, bfin_revid());
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printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
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printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu Mhz System Clock\n",
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cclk / 1000000, sclk / 1000000);
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#if defined(ANOMALY_05000273)
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if ((cclk >> 1) <= sclk)
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printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n");
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#endif
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printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
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printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
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printk(KERN_INFO "Memory map:\n"
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KERN_INFO " text = 0x%p-0x%p\n"
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KERN_INFO " init = 0x%p-0x%p\n"
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KERN_INFO " data = 0x%p-0x%p\n"
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KERN_INFO " stack = 0x%p-0x%p\n"
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KERN_INFO " bss = 0x%p-0x%p\n"
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KERN_INFO " available = 0x%p-0x%p\n"
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#ifdef CONFIG_MTD_UCLINUX
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KERN_INFO " rootfs = 0x%p-0x%p\n"
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#endif
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#if DMA_UNCACHED_REGION > 0
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KERN_INFO " DMA Zone = 0x%p-0x%p\n"
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#endif
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, _stext, _etext,
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__init_begin, __init_end,
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_sdata, _edata,
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(void*)&init_thread_union, (void*)((int)(&init_thread_union) + 0x2000),
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__bss_start, __bss_stop,
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(void*)_ramstart, (void*)memory_end
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#ifdef CONFIG_MTD_UCLINUX
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, (void*)memory_mtd_start, (void*)(memory_mtd_start + mtd_size)
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#endif
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#if DMA_UNCACHED_REGION > 0
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, (void*)(_ramend - DMA_UNCACHED_REGION), (void*)(_ramend)
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#endif
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);
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/*
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* give all the memory to the bootmap allocator, tell it to put the
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* boot mem_map at the start of memory
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*/
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bootmap_size = init_bootmem_node(NODE_DATA(0), memory_start >> PAGE_SHIFT, /* map goes here */
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PAGE_OFFSET >> PAGE_SHIFT,
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memory_end >> PAGE_SHIFT);
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/*
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* free the usable memory, we have to make sure we do not free
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* the bootmem bitmap so we then reserve it after freeing it :-)
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*/
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free_bootmem(memory_start, memory_end - memory_start);
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reserve_bootmem(memory_start, bootmap_size);
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/*
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* get kmalloc into gear
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*/
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paging_init();
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/* check the size of the l1 area */
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l1_length = _etext_l1 - _stext_l1;
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if (l1_length > L1_CODE_LENGTH)
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panic("L1 memory overflow\n");
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l1_length = _ebss_l1 - _sdata_l1;
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if (l1_length > L1_DATA_A_LENGTH)
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panic("L1 memory overflow\n");
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#ifdef BF561_FAMILY
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_bfin_swrst = bfin_read_SICA_SWRST();
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#else
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_bfin_swrst = bfin_read_SWRST();
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#endif
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bf53x_cache_init();
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printk(KERN_INFO "Hardware Trace Enabled\n");
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bfin_write_TBUFCTL(0x03);
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}
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static int __init topology_init(void)
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{
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#if defined (CONFIG_BF561)
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static struct cpu cpu[2];
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register_cpu(&cpu[0], 0);
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register_cpu(&cpu[1], 1);
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return 0;
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#else
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static struct cpu cpu[1];
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return register_cpu(cpu, 0);
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#endif
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}
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subsys_initcall(topology_init);
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#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
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u16 lock_kernel_check(u32 start, u32 end)
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{
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if ((start <= (u32) _stext && end >= (u32) _end)
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|| (start >= (u32) _stext && end <= (u32) _end))
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return IN_KERNEL;
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return 0;
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}
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static unsigned short __init
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fill_cplbtab(struct cplb_tab *table,
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unsigned long start, unsigned long end,
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unsigned long block_size, unsigned long cplb_data)
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{
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int i;
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switch (block_size) {
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case SIZE_4M:
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i = 3;
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break;
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case SIZE_1M:
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i = 2;
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break;
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case SIZE_4K:
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i = 1;
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break;
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case SIZE_1K:
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default:
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i = 0;
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break;
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}
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cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
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while ((start < end) && (table->pos < table->size)) {
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table->tab[table->pos++] = start;
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if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
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table->tab[table->pos++] =
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cplb_data | CPLB_LOCK | CPLB_DIRTY;
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else
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table->tab[table->pos++] = cplb_data;
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start += block_size;
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}
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return 0;
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}
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static unsigned short __init
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close_cplbtab(struct cplb_tab *table)
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{
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while (table->pos < table->size) {
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table->tab[table->pos++] = 0;
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table->tab[table->pos++] = 0; /* !CPLB_VALID */
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}
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return 0;
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}
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static void __init generate_cpl_tables(void)
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{
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u16 i, j, process;
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u32 a_start, a_end, as, ae, as_1m;
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struct cplb_tab *t_i = NULL;
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struct cplb_tab *t_d = NULL;
|
|
struct s_cplb cplb;
|
|
|
|
cplb.init_i.size = MAX_CPLBS;
|
|
cplb.init_d.size = MAX_CPLBS;
|
|
cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
|
|
cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
|
|
|
|
cplb.init_i.pos = 0;
|
|
cplb.init_d.pos = 0;
|
|
cplb.switch_i.pos = 0;
|
|
cplb.switch_d.pos = 0;
|
|
|
|
cplb.init_i.tab = icplb_table;
|
|
cplb.init_d.tab = dcplb_table;
|
|
cplb.switch_i.tab = ipdt_table;
|
|
cplb.switch_d.tab = dpdt_table;
|
|
|
|
cplb_data[SDRAM_KERN].end = memory_end;
|
|
|
|
#ifdef CONFIG_MTD_UCLINUX
|
|
cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
|
|
cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
|
|
cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
|
|
# if defined(CONFIG_ROMFS_FS)
|
|
cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
|
|
|
|
/*
|
|
* The ROMFS_FS size is often not multiple of 1MB.
|
|
* This can cause multiple CPLB sets covering the same memory area.
|
|
* This will then cause multiple CPLB hit exceptions.
|
|
* Workaround: We ensure a contiguous memory area by extending the kernel
|
|
* memory section over the mtd section.
|
|
* For ROMFS_FS memory must be covered with ICPLBs anyways.
|
|
* So there is no difference between kernel and mtd memory setup.
|
|
*/
|
|
|
|
cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
|
|
cplb_data[SDRAM_RAM_MTD].valid = 0;
|
|
|
|
# endif
|
|
#else
|
|
cplb_data[SDRAM_RAM_MTD].valid = 0;
|
|
#endif
|
|
|
|
cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
|
|
cplb_data[SDRAM_DMAZ].end = _ramend;
|
|
|
|
cplb_data[RES_MEM].start = _ramend;
|
|
cplb_data[RES_MEM].end = physical_mem_end;
|
|
|
|
if (reserved_mem_dcache_on)
|
|
cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
|
|
else
|
|
cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
|
|
|
|
if (reserved_mem_icache_on)
|
|
cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
|
|
else
|
|
cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
|
|
|
|
for (i = ZERO_P; i <= L2_MEM; i++) {
|
|
|
|
if (cplb_data[i].valid) {
|
|
|
|
as_1m = cplb_data[i].start % SIZE_1M;
|
|
|
|
/* We need to make sure all sections are properly 1M aligned
|
|
* However between Kernel Memory and the Kernel mtd section, depending on the
|
|
* rootfs size, there can be overlapping memory areas.
|
|
*/
|
|
|
|
if (as_1m && i!=L1I_MEM && i!=L1D_MEM) {
|
|
#ifdef CONFIG_MTD_UCLINUX
|
|
if (i == SDRAM_RAM_MTD) {
|
|
if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
|
|
cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
|
|
else
|
|
cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
|
|
} else
|
|
#endif
|
|
printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
|
|
cplb_data[i].name, cplb_data[i].start);
|
|
}
|
|
|
|
as = cplb_data[i].start % SIZE_4M;
|
|
ae = cplb_data[i].end % SIZE_4M;
|
|
|
|
if (as)
|
|
a_start = cplb_data[i].start + (SIZE_4M - (as));
|
|
else
|
|
a_start = cplb_data[i].start;
|
|
|
|
a_end = cplb_data[i].end - ae;
|
|
|
|
for (j = INITIAL_T; j <= SWITCH_T; j++) {
|
|
|
|
switch (j) {
|
|
case INITIAL_T:
|
|
if (cplb_data[i].attr & INITIAL_T) {
|
|
t_i = &cplb.init_i;
|
|
t_d = &cplb.init_d;
|
|
process = 1;
|
|
} else
|
|
process = 0;
|
|
break;
|
|
case SWITCH_T:
|
|
if (cplb_data[i].attr & SWITCH_T) {
|
|
t_i = &cplb.switch_i;
|
|
t_d = &cplb.switch_d;
|
|
process = 1;
|
|
} else
|
|
process = 0;
|
|
break;
|
|
default:
|
|
process = 0;
|
|
break;
|
|
}
|
|
|
|
if (process) {
|
|
if (cplb_data[i].attr & I_CPLB) {
|
|
|
|
if (cplb_data[i].psize) {
|
|
fill_cplbtab(t_i,
|
|
cplb_data[i].start,
|
|
cplb_data[i].end,
|
|
cplb_data[i].psize,
|
|
cplb_data[i].i_conf);
|
|
} else {
|
|
/*icplb_table */
|
|
#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
|
|
if (i == SDRAM_KERN) {
|
|
fill_cplbtab(t_i,
|
|
cplb_data[i].start,
|
|
cplb_data[i].end,
|
|
SIZE_4M,
|
|
cplb_data[i].i_conf);
|
|
} else
|
|
#endif
|
|
{
|
|
fill_cplbtab(t_i,
|
|
cplb_data[i].start,
|
|
a_start,
|
|
SIZE_1M,
|
|
cplb_data[i].i_conf);
|
|
fill_cplbtab(t_i,
|
|
a_start,
|
|
a_end,
|
|
SIZE_4M,
|
|
cplb_data[i].i_conf);
|
|
fill_cplbtab(t_i, a_end,
|
|
cplb_data[i].end,
|
|
SIZE_1M,
|
|
cplb_data[i].i_conf);
|
|
}
|
|
}
|
|
|
|
}
|
|
if (cplb_data[i].attr & D_CPLB) {
|
|
|
|
if (cplb_data[i].psize) {
|
|
fill_cplbtab(t_d,
|
|
cplb_data[i].start,
|
|
cplb_data[i].end,
|
|
cplb_data[i].psize,
|
|
cplb_data[i].d_conf);
|
|
} else {
|
|
/*dcplb_table*/
|
|
fill_cplbtab(t_d,
|
|
cplb_data[i].start,
|
|
a_start, SIZE_1M,
|
|
cplb_data[i].d_conf);
|
|
fill_cplbtab(t_d, a_start,
|
|
a_end, SIZE_4M,
|
|
cplb_data[i].d_conf);
|
|
fill_cplbtab(t_d, a_end,
|
|
cplb_data[i].end,
|
|
SIZE_1M,
|
|
cplb_data[i].d_conf);
|
|
|
|
}
|
|
|
|
}
|
|
}
|
|
}
|
|
|
|
}
|
|
}
|
|
|
|
/* close tables */
|
|
|
|
close_cplbtab(&cplb.init_i);
|
|
close_cplbtab(&cplb.init_d);
|
|
|
|
cplb.init_i.tab[cplb.init_i.pos] = -1;
|
|
cplb.init_d.tab[cplb.init_d.pos] = -1;
|
|
cplb.switch_i.tab[cplb.switch_i.pos] = -1;
|
|
cplb.switch_d.tab[cplb.switch_d.pos] = -1;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
static inline u_long get_vco(void)
|
|
{
|
|
u_long msel;
|
|
u_long vco;
|
|
|
|
msel = (bfin_read_PLL_CTL() >> 9) & 0x3F;
|
|
if (0 == msel)
|
|
msel = 64;
|
|
|
|
vco = CONFIG_CLKIN_HZ;
|
|
vco >>= (1 & bfin_read_PLL_CTL()); /* DF bit */
|
|
vco = msel * vco;
|
|
return vco;
|
|
}
|
|
|
|
/*Get the Core clock*/
|
|
u_long get_cclk(void)
|
|
{
|
|
u_long csel, ssel;
|
|
if (bfin_read_PLL_STAT() & 0x1)
|
|
return CONFIG_CLKIN_HZ;
|
|
|
|
ssel = bfin_read_PLL_DIV();
|
|
csel = ((ssel >> 4) & 0x03);
|
|
ssel &= 0xf;
|
|
if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
|
|
return get_vco() / ssel;
|
|
return get_vco() >> csel;
|
|
}
|
|
|
|
EXPORT_SYMBOL(get_cclk);
|
|
|
|
/* Get the System clock */
|
|
u_long get_sclk(void)
|
|
{
|
|
u_long ssel;
|
|
|
|
if (bfin_read_PLL_STAT() & 0x1)
|
|
return CONFIG_CLKIN_HZ;
|
|
|
|
ssel = (bfin_read_PLL_DIV() & 0xf);
|
|
if (0 == ssel) {
|
|
printk(KERN_WARNING "Invalid System Clock\n");
|
|
ssel = 1;
|
|
}
|
|
|
|
return get_vco() / ssel;
|
|
}
|
|
|
|
EXPORT_SYMBOL(get_sclk);
|
|
|
|
/*
|
|
* Get CPU information for use by the procfs.
|
|
*/
|
|
static int show_cpuinfo(struct seq_file *m, void *v)
|
|
{
|
|
char *cpu, *mmu, *fpu, *name;
|
|
uint32_t revid;
|
|
|
|
u_long cclk = 0, sclk = 0;
|
|
u_int dcache_size = 0, dsup_banks = 0;
|
|
|
|
cpu = CPU;
|
|
mmu = "none";
|
|
fpu = "none";
|
|
revid = bfin_revid();
|
|
name = bfin_board_name;
|
|
|
|
cclk = get_cclk();
|
|
sclk = get_sclk();
|
|
|
|
seq_printf(m, "CPU:\t\tADSP-%s Rev. 0.%d\n"
|
|
"MMU:\t\t%s\n"
|
|
"FPU:\t\t%s\n"
|
|
"Core Clock:\t%9lu Hz\n"
|
|
"System Clock:\t%9lu Hz\n"
|
|
"BogoMips:\t%lu.%02lu\n"
|
|
"Calibration:\t%lu loops\n",
|
|
cpu, revid, mmu, fpu,
|
|
cclk,
|
|
sclk,
|
|
(loops_per_jiffy * HZ) / 500000,
|
|
((loops_per_jiffy * HZ) / 5000) % 100,
|
|
(loops_per_jiffy * HZ));
|
|
seq_printf(m, "Board Name:\t%s\n", name);
|
|
seq_printf(m, "Board Memory:\t%ld MB\n", physical_mem_end >> 20);
|
|
seq_printf(m, "Kernel Memory:\t%ld MB\n", (unsigned long)_ramend >> 20);
|
|
if (bfin_read_IMEM_CONTROL() & (ENICPLB | IMC))
|
|
seq_printf(m, "I-CACHE:\tON\n");
|
|
else
|
|
seq_printf(m, "I-CACHE:\tOFF\n");
|
|
if ((bfin_read_DMEM_CONTROL()) & (ENDCPLB | DMC_ENABLE))
|
|
seq_printf(m, "D-CACHE:\tON"
|
|
#if defined CONFIG_BLKFIN_WB
|
|
" (write-back)"
|
|
#elif defined CONFIG_BLKFIN_WT
|
|
" (write-through)"
|
|
#endif
|
|
"\n");
|
|
else
|
|
seq_printf(m, "D-CACHE:\tOFF\n");
|
|
|
|
|
|
switch(bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) {
|
|
case ACACHE_BSRAM:
|
|
seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tSRAM\n");
|
|
dcache_size = 16;
|
|
dsup_banks = 1;
|
|
break;
|
|
case ACACHE_BCACHE:
|
|
seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tCACHE\n");
|
|
dcache_size = 32;
|
|
dsup_banks = 2;
|
|
break;
|
|
case ASRAM_BSRAM:
|
|
seq_printf(m, "DBANK-A:\tSRAM\n" "DBANK-B:\tSRAM\n");
|
|
dcache_size = 0;
|
|
dsup_banks = 0;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
|
|
seq_printf(m, "I-CACHE Size:\t%dKB\n", BLKFIN_ICACHESIZE / 1024);
|
|
seq_printf(m, "D-CACHE Size:\t%dKB\n", dcache_size);
|
|
seq_printf(m, "I-CACHE Setup:\t%d Sub-banks/%d Ways, %d Lines/Way\n",
|
|
BLKFIN_ISUBBANKS, BLKFIN_IWAYS, BLKFIN_ILINES);
|
|
seq_printf(m,
|
|
"D-CACHE Setup:\t%d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
|
|
dsup_banks, BLKFIN_DSUBBANKS, BLKFIN_DWAYS,
|
|
BLKFIN_DLINES);
|
|
#ifdef CONFIG_BLKFIN_CACHE_LOCK
|
|
switch (read_iloc()) {
|
|
case WAY0_L:
|
|
seq_printf(m, "Way0 Locked-Down\n");
|
|
break;
|
|
case WAY1_L:
|
|
seq_printf(m, "Way1 Locked-Down\n");
|
|
break;
|
|
case WAY01_L:
|
|
seq_printf(m, "Way0,Way1 Locked-Down\n");
|
|
break;
|
|
case WAY2_L:
|
|
seq_printf(m, "Way2 Locked-Down\n");
|
|
break;
|
|
case WAY02_L:
|
|
seq_printf(m, "Way0,Way2 Locked-Down\n");
|
|
break;
|
|
case WAY12_L:
|
|
seq_printf(m, "Way1,Way2 Locked-Down\n");
|
|
break;
|
|
case WAY012_L:
|
|
seq_printf(m, "Way0,Way1 & Way2 Locked-Down\n");
|
|
break;
|
|
case WAY3_L:
|
|
seq_printf(m, "Way3 Locked-Down\n");
|
|
break;
|
|
case WAY03_L:
|
|
seq_printf(m, "Way0,Way3 Locked-Down\n");
|
|
break;
|
|
case WAY13_L:
|
|
seq_printf(m, "Way1,Way3 Locked-Down\n");
|
|
break;
|
|
case WAY013_L:
|
|
seq_printf(m, "Way 0,Way1,Way3 Locked-Down\n");
|
|
break;
|
|
case WAY32_L:
|
|
seq_printf(m, "Way3,Way2 Locked-Down\n");
|
|
break;
|
|
case WAY320_L:
|
|
seq_printf(m, "Way3,Way2,Way0 Locked-Down\n");
|
|
break;
|
|
case WAY321_L:
|
|
seq_printf(m, "Way3,Way2,Way1 Locked-Down\n");
|
|
break;
|
|
case WAYALL_L:
|
|
seq_printf(m, "All Ways are locked\n");
|
|
break;
|
|
default:
|
|
seq_printf(m, "No Ways are locked\n");
|
|
}
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
static void *c_start(struct seq_file *m, loff_t *pos)
|
|
{
|
|
return *pos < NR_CPUS ? ((void *)0x12345678) : NULL;
|
|
}
|
|
|
|
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
|
|
{
|
|
++*pos;
|
|
return c_start(m, pos);
|
|
}
|
|
|
|
static void c_stop(struct seq_file *m, void *v)
|
|
{
|
|
}
|
|
|
|
struct seq_operations cpuinfo_op = {
|
|
.start = c_start,
|
|
.next = c_next,
|
|
.stop = c_stop,
|
|
.show = show_cpuinfo,
|
|
};
|
|
|
|
void cmdline_init(unsigned long r0)
|
|
{
|
|
if (r0)
|
|
strncpy(command_line, (char *)r0, COMMAND_LINE_SIZE);
|
|
}
|