forked from Minki/linux
0807da5938
Let's handle GPIOs by banks, each bank covers up to 32 GPIOs with one set
of registers, and each set of registers start from different offsets.
GPLR GPDR GPSR GPCR GRER GFER GEDR
BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
NOTE:
BANK 3 is only available on PXA27x and later processors.
BANK 4 and 5 are only available on PXA935
1. introduce GPIO_BANK(n) for the offset base of each bank
2. 'struct pxa_gpio_chip' is expanded to include IRQ edge and mask
setings, and saved register values as well, and is dynamically
allocated due to possible bank number ranging from 3 to 6
3. all accesses to GPIO registers are made through 'regbase' within
'pxa_gpio_chip', and register offset
4. introduce several inline functions to simplify the code a bit
5. change IRQ demux handler to base on gpio chips
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
172 lines
5.4 KiB
C
172 lines
5.4 KiB
C
/*
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* arch/arm/mach-pxa/include/mach/gpio.h
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*
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* PXA GPIO wrappers for arch-neutral GPIO calls
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*
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* Written by Philipp Zabel <philipp.zabel@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef __ASM_ARCH_PXA_GPIO_H
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#define __ASM_ARCH_PXA_GPIO_H
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#include <mach/irqs.h>
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#include <mach/hardware.h>
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#include <asm-generic/gpio.h>
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#define GPIO_REGS_VIRT io_p2v(0x40E00000)
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#define BANK_OFF(n) (((n) > 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
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#define GPIO_REG(x) (*(volatile u32 *)(GPIO_REGS_VIRT + (x)))
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/* GPIO Pin Level Registers */
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#define GPLR0 GPIO_REG(BANK_OFF(0) + 0x00)
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#define GPLR1 GPIO_REG(BANK_OFF(1) + 0x00)
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#define GPLR2 GPIO_REG(BANK_OFF(2) + 0x00)
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#define GPLR3 GPIO_REG(BANK_OFF(3) + 0x00)
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/* GPIO Pin Direction Registers */
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#define GPDR0 GPIO_REG(BANK_OFF(0) + 0x0c)
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#define GPDR1 GPIO_REG(BANK_OFF(1) + 0x0c)
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#define GPDR2 GPIO_REG(BANK_OFF(2) + 0x0c)
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#define GPDR3 GPIO_REG(BANK_OFF(3) + 0x0c)
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/* GPIO Pin Output Set Registers */
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#define GPSR0 GPIO_REG(BANK_OFF(0) + 0x18)
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#define GPSR1 GPIO_REG(BANK_OFF(1) + 0x18)
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#define GPSR2 GPIO_REG(BANK_OFF(2) + 0x18)
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#define GPSR3 GPIO_REG(BANK_OFF(3) + 0x18)
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/* GPIO Pin Output Clear Registers */
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#define GPCR0 GPIO_REG(BANK_OFF(0) + 0x24)
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#define GPCR1 GPIO_REG(BANK_OFF(1) + 0x24)
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#define GPCR2 GPIO_REG(BANK_OFF(2) + 0x24)
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#define GPCR3 GPIO_REG(BANK_OFF(3) + 0x24)
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/* GPIO Rising Edge Detect Registers */
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#define GRER0 GPIO_REG(BANK_OFF(0) + 0x30)
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#define GRER1 GPIO_REG(BANK_OFF(1) + 0x30)
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#define GRER2 GPIO_REG(BANK_OFF(2) + 0x30)
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#define GRER3 GPIO_REG(BANK_OFF(3) + 0x30)
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/* GPIO Falling Edge Detect Registers */
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#define GFER0 GPIO_REG(BANK_OFF(0) + 0x3c)
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#define GFER1 GPIO_REG(BANK_OFF(1) + 0x3c)
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#define GFER2 GPIO_REG(BANK_OFF(2) + 0x3c)
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#define GFER3 GPIO_REG(BANK_OFF(3) + 0x3c)
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/* GPIO Edge Detect Status Registers */
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#define GEDR0 GPIO_REG(BANK_OFF(0) + 0x48)
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#define GEDR1 GPIO_REG(BANK_OFF(1) + 0x48)
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#define GEDR2 GPIO_REG(BANK_OFF(2) + 0x48)
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#define GEDR3 GPIO_REG(BANK_OFF(3) + 0x48)
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/* GPIO Alternate Function Select Registers */
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#define GAFR0_L GPIO_REG(0x0054)
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#define GAFR0_U GPIO_REG(0x0058)
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#define GAFR1_L GPIO_REG(0x005C)
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#define GAFR1_U GPIO_REG(0x0060)
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#define GAFR2_L GPIO_REG(0x0064)
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#define GAFR2_U GPIO_REG(0x0068)
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#define GAFR3_L GPIO_REG(0x006C)
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#define GAFR3_U GPIO_REG(0x0070)
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/* More handy macros. The argument is a literal GPIO number. */
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#define GPIO_bit(x) (1 << ((x) & 0x1f))
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#define GPLR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x00)
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#define GPDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x0c)
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#define GPSR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x18)
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#define GPCR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x24)
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#define GRER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x30)
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#define GFER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x3c)
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#define GEDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x48)
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#define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2))
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/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
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* Those cases currently cause holes in the GPIO number space, the
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* actual number of the last GPIO is recorded by 'pxa_last_gpio'.
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*/
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extern int pxa_last_gpio;
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#define NR_BUILTIN_GPIO 128
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static inline int gpio_get_value(unsigned gpio)
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{
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if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO))
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return GPLR(gpio) & GPIO_bit(gpio);
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else
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return __gpio_get_value(gpio);
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}
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static inline void gpio_set_value(unsigned gpio, int value)
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{
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if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) {
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if (value)
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GPSR(gpio) = GPIO_bit(gpio);
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else
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GPCR(gpio) = GPIO_bit(gpio);
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} else {
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__gpio_set_value(gpio, value);
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}
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}
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#define gpio_cansleep __gpio_cansleep
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#define gpio_to_bank(gpio) ((gpio) >> 5)
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#define gpio_to_irq(gpio) IRQ_GPIO(gpio)
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#define irq_to_gpio(irq) IRQ_TO_GPIO(irq)
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#ifdef CONFIG_CPU_PXA26x
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/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted,
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* as well as their Alternate Function value being '1' for GPIO in GAFRx.
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*/
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static inline int __gpio_is_inverted(unsigned gpio)
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{
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return cpu_is_pxa25x() && gpio > 85;
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}
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#else
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static inline int __gpio_is_inverted(unsigned gpio) { return 0; }
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#endif
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/*
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* On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
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* function of a GPIO, and GPDRx cannot be altered once configured. It
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* is attributed as "occupied" here (I know this terminology isn't
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* accurate, you are welcome to propose a better one :-)
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*/
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static inline int __gpio_is_occupied(unsigned gpio)
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{
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if (cpu_is_pxa27x() || cpu_is_pxa25x()) {
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int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3;
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int dir = GPDR(gpio) & GPIO_bit(gpio);
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if (__gpio_is_inverted(gpio))
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return af != 1 || dir == 0;
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else
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return af != 0 || dir != 0;
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} else
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return GPDR(gpio) & GPIO_bit(gpio);
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}
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typedef int (*set_wake_t)(unsigned int irq, unsigned int on);
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extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn);
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#endif
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