forked from Minki/linux
3d5e2abe6e
This patch sets HPM (Host power mask bit) to bit 16 according to i.MX Reference Manual. Falsely it was set to bit 8, but this controls pull-up Impedance. Reported-by: Michael Burkey <mdburkey@gmail.com> Cc: Stable <stable@vger.kernel.org> Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com> Acked-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
98 lines
2.7 KiB
C
98 lines
2.7 KiB
C
/*
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* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
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* Copyright (C) 2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <linux/platform_data/usb-ehci-mxc.h>
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#define USBCTRL_OTGBASE_OFFSET 0x600
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#define MX35_OTG_SIC_SHIFT 29
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#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
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#define MX35_OTG_PM_BIT (1 << 24)
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#define MX35_OTG_PP_BIT (1 << 11)
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#define MX35_OTG_OCPOL_BIT (1 << 3)
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#define MX35_H1_SIC_SHIFT 21
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#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
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#define MX35_H1_PP_BIT (1 << 18)
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#define MX35_H1_PM_BIT (1 << 16)
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#define MX35_H1_IPPUE_UP_BIT (1 << 7)
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#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
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#define MX35_H1_TLL_BIT (1 << 5)
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#define MX35_H1_USBTE_BIT (1 << 4)
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#define MX35_H1_OCPOL_BIT (1 << 2)
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int mx35_initialize_usb_hw(int port, unsigned int flags)
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{
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unsigned int v;
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v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
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switch (port) {
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case 0: /* OTG port */
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v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
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MX35_OTG_OCPOL_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX35_OTG_PM_BIT;
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MX35_OTG_PP_BIT;
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if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
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v |= MX35_OTG_OCPOL_BIT;
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break;
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case 1: /* H1 port */
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v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
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MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT |
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MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX35_H1_PM_BIT;
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MX35_H1_PP_BIT;
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if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
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v |= MX35_H1_OCPOL_BIT;
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if (!(flags & MXC_EHCI_TTL_ENABLED))
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v |= MX35_H1_TLL_BIT;
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if (flags & MXC_EHCI_INTERNAL_PHY)
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v |= MX35_H1_USBTE_BIT;
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if (flags & MXC_EHCI_IPPUE_DOWN)
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v |= MX35_H1_IPPUE_DOWN_BIT;
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if (flags & MXC_EHCI_IPPUE_UP)
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v |= MX35_H1_IPPUE_UP_BIT;
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break;
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default:
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return -EINVAL;
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}
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writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
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return 0;
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}
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